- 27 Oct, 2020 38 commits
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Evan Quan authored
Correct the mclk switching setting for multiple displays. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Evan Quan authored
Enable watermark table setting for Polaris. Signed-off-by:
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Evan Quan authored
Fulfill Polaris get_clock_by_type_with_latency(). Signed-off-by:
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Evan Quan authored
Correct Polaris10 setup. Signed-off-by:
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Evan Quan authored
Correct Polaris smc boot level setup. Signed-off-by:
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Evan Quan authored
Correct Polaris10 pcie spc cap setting. Signed-off-by:
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Evan Quan authored
Correct Polaris10 clk/voltage dependence setup. Signed-off-by:
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Evan Quan authored
Populate the correct highest vddc setting on Polaris. Signed-off-by:
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Evan Quan authored
Correct Polaris10 sclk/mclk dpm enablement. Signed-off-by:
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Evan Quan authored
Correct Polaris10 smc voltage controller setup. Signed-off-by:
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Evan Quan authored
Correct Polaris10 platformcaps setup. Signed-off-by:
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Evan Quan authored
Correct Polaris VRconfig setting. Signed-off-by:
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Evan Quan authored
Correct Polaris10 vddc phase control. Signed-off-by:
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Evan Quan authored
Correct Polaris10 avfs fuse setting. Signed-off-by:
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Evan Quan authored
Correct Polaris DIDT enablement. Signed-off-by:
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Evan Quan authored
Correct powertune table setup for Polaris. Signed-off-by:
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Evan Quan authored
Correct sclk/mclk SS support checks. Signed-off-by:
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Evan Quan authored
Add VR shared rail info. Signed-off-by:
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Evan Quan authored
Add mc register table initialization. Signed-off-by:
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Evan Quan authored
Enable edc controller table setting. Signed-off-by:
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Evan Quan authored
Only if the ZeroRPM feature is supported. Signed-off-by:
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Evan Quan authored
By using the saved copy of ro_range_maximum and ro_range_minimum. Correct the setting for "LdoRefSel". Signed-off-by:
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Evan Quan authored
Make the settings more precise. Signed-off-by:
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Evan Quan authored
By moving that in atomfw_read_efuse(). Signed-off-by:
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Evan Quan authored
Programming AC Timing Parameters is only dependent on MCLK. No need to nest loop for each SCLK DPM level. Signed-off-by:
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Evan Quan authored
Instead of sharing the fan table setup with Tonga, Polaris has its own fan table setup. Signed-off-by:
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Evan Quan authored
This is for some special Polaris10 ASICs. Signed-off-by:
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Evan Quan authored
Correct polaris CG_ACLK_CNTL setting. Signed-off-by:
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Evan Quan authored
As this is not needed for polaris. Signed-off-by:
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Evan Quan authored
Add missing VRHotLevel setting. Signed-off-by:
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Evan Quan authored
Set the BootLinkLevel as the max level. Signed-off-by:
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Evan Quan authored
Correct the setting for "ActivityLevel". V2: rich the comment Signed-off-by:
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Evan Quan authored
Correct the settings for "StutterEnable" and "EnabledForActivity". Signed-off-by:
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Evan Quan authored
Correct Polaris10 sclk table setup. Signed-off-by:
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Evan Quan authored
Make sure the settings are applied only when voltage controlled by gpio. Signed-off-by:
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Evan Quan authored
Add missing smc samu table setup. Signed-off-by:
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Evan Quan authored
Add missing vddc table setup. Signed-off-by:
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Evan Quan authored
By defining new Macros. Signed-off-by:
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- 26 Oct, 2020 2 commits
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Takashi Iwai authored
This patch simplifies the ASSERT*() and BREAK_TO_DEBUGGER() macros: - Move the dependency check of CONFIG_KGDB into Kconfig - Unify the kgdb_breakpoint() call - Drop the non-existing CONFIG_HAVE_KGDB Also align the behavior of ASSERT() macro in both cases with and without CONFIG_DEBUG_KERNEL_DC. Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Takashi Iwai authored
ASSERT_CRITICAL() invokes kgdb_breakpoint() whenever either CONFIG_KGDB or CONFIG_HAVE_KGDB is set. This, however, may lead to a kernel panic when no kdb stuff is attached, since the kgdb_breakpoint() call issues INT3. It's nothing but a surprise for normal end-users. For avoiding the pitfall, make the kgdb_breakpoint() call only when CONFIG_DEBUG_KERNEL_DC is set. https://bugzilla.opensuse.org/show_bug.cgi?id=1177973 Cc: <stable@vger.kernel.org> Acked-by:
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