- 19 Nov, 2012 4 commits
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Ludovic Desroches authored
Add mci controller nodes to atmel boards. Signed-off-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Ludovic Desroches authored
Add mci controller nodes to atmel SOCs. Signed-off-by:
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Ludovic Desroches authored
Add clocks to clock lookup table for DT entries. Signed-off-by:
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- 21 Nov, 2012 1 commit
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- 18 Nov, 2012 13 commits
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by: -
Joachim Eastwood authored
Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
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Joachim Eastwood authored
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Joachim Eastwood authored
Signed-off-by:
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Joachim Eastwood authored
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Joachim Eastwood authored
Based on AT91 PIT DT patch from Jean-Christophe PLAGNIOL-VILLARD. Signed-off-by:
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Joachim Eastwood authored
We need CONFIG_SOC_AT91SAM9 to get the at91sam926x_timer symbol used in board-dt. Signed-off-by:
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Jean-Christophe PLAGNIOL-VILLARD authored
CPU Module with ATMEL AT91SAM9G45 http://www.ronetix.at/pm9g45.htmlSigned-off-by:
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Jean-Christophe PLAGNIOL-VILLARD authored
as we just use the rts and not the rts & cts for rs485 Signed-off-by: -
Jean-Christophe PLAGNIOL-VILLARD authored
USART are the full pin uart DBGU the debug Unit UART the two pin uart Signed-off-by: -
Jean-Christophe PLAGNIOL-VILLARD authored
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Jean-Christophe PLAGNIOL-VILLARD authored
add : set_deglitch: enable/disable deglitch set_debounce: enable/disable debounce set_pulldown: enable/disable pulldown disable_schmitt_trig: disable schmitt trigger Signed-off-by: -
Jean-Christophe PLAGNIOL-VILLARD authored
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- 11 Nov, 2012 22 commits
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Linus Walleij authored
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Viresh Kumar authored
This patch adds plgpio nodes in SPEAr DT files. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Viresh Kumar authored
Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio. This patch gpio enable support for SPEAr pinctrl drivers. Signed-off-by:
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Linus Walleij authored
The <*/gpio.h> includes are updated again: now we need to account for the problem introduced by commit: 595679a8038584df7b9398bf34f61db3c038bfea "gpiolib: fix up function prototypes etc" Actually we need static inlines in include/asm-generic/gpio.h as well since we may have GPIOLIB but not PINCTRL. Make sure to move all the CONFIG_PINCTRL business to the end of the file so we are sure we have declared struct gpio_chip. And we need to keep the static inlines in <linux/gpio.h> but here for the !CONFIG_GENERIC_GPIO case, and then we may as well throw in a few warnings like the other prototypes there, if someone would have the bad taste of compiling without GENERIC_GPIO even. Signed-off-by: -
Linus Walleij authored
The fact that of_gpiochip_add_pin_range() and gpiochip_add_pin_range() share too much code is fragile and will invariably mean that bugs need to be fixed in two places instead of one. So separate the concerns of gpiolib.c and gpiolib-of.c and have the latter call the former as back-end. This is necessary also when going forward with other device descriptions such as ACPI. This is done by: - Adding a return code to gpiochip_add_pin_range() so we can reliably check whether this succeeds. - Get rid of the custom of_pinctrl_add_gpio_range() from pinctrl. Instead create of_pinctrl_get() to just retrive the pin controller per se from an OF node. This composite function was just begging to be deleted, it was way to purpose-specific. - Use pinctrl_dev_get_name() to get the name of the retrieved pin controller and use that to call back into the generic gpiochip_add_pin_range(). Now the pin range is only allocated and tied to a pin controller from the core implementation in gpiolib.c. Signed-off-by: -
Linus Walleij authored
This makes us call gpiochio_remove_pin_ranges() in the gpiochip_remove() function, so we get rid of ranges when freeing the chip. Reviewed-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
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Linus Walleij authored
Commit 69e1601bca88809dc118abd1becb02c15a02ec71 "gpiolib: provide provision to register pin ranges" Introduced both of_gpiochip_remove_pin_range() and gpiochip_remove_pin_ranges(). But the contents are exactly the same so remove the OF one and rely on the range deletion in the core. Reviewed-by:
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Linus Walleij authored
Commit 69e1601bca88809dc118abd1becb02c15a02ec71 "gpiolib: provide provision to register pin ranges" Declared the of_gpiochip_[add|remove]_pin_range() global while they should be static as they are only ever used in this file. Let's convert them to static. Reviewed-by:
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Linus Walleij authored
Commit 69e1601bca88809dc118abd1becb02c15a02ec71 "gpiolib: provide provision to register pin ranges" Got most of it's function prototypes wrong, so fix this up by: - Moving the void declarations into static inlines in <linux/gpio.h> (previously the actual prototypes were declared here...) - Declare the gpiochip_add_pin_range() and gpiochip_remove_pin_ranges() functions in <asm-generic/gpio.h> together with the pin range struct declaration itself. - Actually only implement these very functions in gpiolib.c if CONFIG_PINCTRL is set. - Additionally export the symbols since modules will need to be able to do this. Reviewed-by:
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Axel Lin authored
Staticize sirfsoc_gpio_irq_map() function. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Axel Lin authored
Staticize u300_pin_config_get() and u300_pin_config_set() functions. Signed-off-by:
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Linus Walleij authored
This converts the U300 pin controller to use managed resources (devm_*) for it's memory region. Signed-off-by: -
Linus Walleij authored
This switches the COH 901 pin controller to use managed resources (devm_*) for memory remaps, clocks, etc. Signed-off-by: -
Linus Walleij authored
This switches the COH 901 pinctrl driver to allocate its GPIO IRQs dynamically, and start to use a linear irqdomain to map from the hardware IRQs. This way we can cut away the complex allocation of IRQ numbers from the <mach/irqs.h> file. Signed-off-by: -
Linus Walleij authored
The U300 IRQs were bumped once to offset to 1 (in order to avoid using IRQ 0 which is now NO_IRQ). This was OK as we were still passing the number of irqs in the .nr_irqs field of the machine, with descriptors allocated at boot time. However .nr_irqs should be 0, leading the system to reserve the first 16 IRQs. Then the VIC driver will complain that IRQs 1 thru 15 are pre-allocated, so to avoid this and use free descriptors, move all IRQs up to offset 32. This will all be done away with as we migrate to device tree, so it is an interim solution. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
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Viresh Kumar authored
Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio. This patch adds plgpio driver for configuring these pads as gpio. Signed-off-by:
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Shiraz Hashim authored
pinctrl subsystem needs gpio chip base to prepare set of gpio pin ranges, which a given pinctrl driver can handle. This is important to handle pinctrl gpio request calls in order to program a given pin properly for gpio operation. As gpio base is allocated dynamically during gpiochip registration, presently there exists no clean way to pass this information to the pinctrl subsystem. After few discussions from [1], it was concluded that may be gpio controller reporting the pin range it supports, is a better way than pinctrl subsystem directly registering it. [1] http://comments.gmane.org/gmane.linux.ports.arm.kernel/184816 Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
Shiraz Hashim <shiraz.hashim@st.com> [Edited documentation a bit] Signed-off-by:
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Viresh Kumar authored
This reverts earlier commit which removed pinctrl_remove_gpio_range(), because at that time there weren't any more users of that routine. It was removed as the removal of ranges was done in unregister of pinctrl. But as we are now registering stuff from gpiolib, we may remove and insert a gpio module multiple times. So, we need this routine again. Signed-off-by:
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Axel Lin authored
The of_device_id table is supposed to be zero-terminated. Signed-off-by:
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Barry Song authored
The driver supports old up SiRFprimaII SoCs, this patch makes it support the new SiRFmarco as well. SiRFmarco, as a SMP SoC, adds new SIRFSOC_GPIO_PAD_EN_CLR registers, to disable GPIO pad, we should write 1 to the corresponding bit in the new CLEAR register instead of writing 0 to SIRFSOC_GPIO_PAD_EN. Signed-off-by:
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Thomas Petazzoni authored
Like the spear platform, the mvebu platform has multiple files: one core file, and then one file per SoC family. More files will be added later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to pinctrl-mvebu. For those reasons, having a separate subdirectory, drivers/pinctrl/mvebu/ makes sense, and it had already been suggested by Linus Wallej when the driver was originally submitted. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Thomas Petazzoni authored
Including the core.h header for the pinctrl subsystem is not necessary, and it is actually causing problems when moving the pinctrl-mvebu drivers into a separate subdirectory. Signed-off-by:
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