- 05 May, 2016 40 commits
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Alex Deucher authored
Add support for the display configuration on elm/baf. v2: add missing Stoney case Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com>
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Alex Deucher authored
New asic types for ellesmere and baffin. Reviewed-by:
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Alex Deucher authored
Add register headers for DCE (Display and Composition Engine) 11.2. Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Acked-by:
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Bas Nieuwenhuizen authored
Mesa uses a COPY_DATA packet to copy the grid size for indirect dispatches into COMPUTE_USER_DATA_*. Setting those registers with a SET_SH_REG packet is allowed, not allowing them with other packets seems like an oversight. v2: Clarify commit message. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Christian König authored
Not needed any more. Signed-off-by:
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Christian König authored
This allows us to have small BOs on the LRU before big ones. v2: fix of by one and list corruption bug Signed-off-by:
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Dave Airlie authored
This isn't being used so drop it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
we introduced vmid fence, so one hw submission could produce two fences. Signed-off-by:
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Alex Deucher authored
Acked-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
They care common for all sdma 3.0 parts Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
They can be used for other VI parts. Acked-by:
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Alex Deucher authored
v2: just enable MGCG for now since CGCG causes hangs Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
They can be shared with other asics with minor modifications. Acked-by:
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Alex Deucher authored
Different asics tend to have different ways to interact with the RLC. This just covers enter/exit of safe mode for updating CG and PG state, but could be extended to cover other RLC operations in the future if necessary. Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
So it can be shared with CZ/ST. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
Acked-by:
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Christian König authored
This allows fine grained control for the driver where to add a BO into the LRU. v2: fix typo in comment Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Signed-off-by:
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Christian König authored
Useful for driver specific LRU handling. v2: fix typo in comment Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
When we use an extern reservation object that otherwise waits for every fence registered with it. Reviewed-by:
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Christian König authored
No functional change. Signed-off-by:
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Christian König authored
Instead of hard coding just another name in the ring code. v2: squash in Tom's rebase fix Signed-off-by:
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Christian König authored
Those are way too large. Signed-off-by:
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Christian König authored
Those are way too large. Signed-off-by:
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Christian König authored
Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by:
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Eric Huang authored
Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
Signed-off-by:
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