1. 01 Nov, 2006 37 commits
  2. 31 Oct, 2006 3 commits
    • Keith Owens's avatar
      [IA64] Correct definition of handle_IPI · 024e4f2c
      Keith Owens authored
      The declaration of handle_IPI in arch/ia64/kernel/smp.c was changed but
      not the definition of this function.  Remove struct pt_regs from
      handle_IPI().
      Signed-off-by: default avatarKeith Owens <kaos@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      024e4f2c
    • Troy Heber's avatar
      [IA64] move SAL_CACHE_FLUSH check later in boot · fa1d19e5
      Troy Heber authored
      The check to see if the firmware drops interrupts during a
      SAL_CACHE_FLUSH is done to early in the boot. SAL_CACHE_FLUSH expects
      to be able to make PAL calls in virtual mode, on some cell based
      machines a fault occurs causing a MCA. This patch moves the check
      after mmu_context_init so the TLB and VHPT are properly setup.
      
      Signed-off-by Troy Heber <troy.heber@hp.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      fa1d19e5
    • Russ Anderson's avatar
      [IA64] MCA recovery: Montecito support · 264b0f99
      Russ Anderson authored
      The information in MCA records is filled in slightly differently on
      Montecito than on Madison/McKinley.  Usually, the cache check and bus
      check target identifiers have the same address.   On Montecito the
      cache check and bus check target identifiers can be different if 
      a corrected error (ie SBE or unconsumed poison data) was encountered and
      then an uncorrected error (ie DBE) was consumed.  In that case, the 
      cache check target identifier is the physical address of the DBE (that
      caused the MCA to surface) while the bus check target identifier is the 
      physical address of the SBE.  This patch correctly finds the target
      identifier that triggered the MCA.
      
      If there are multiple valid cache target identifiers in the same
      error record then use the one with the lowest cache level.
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      264b0f99