- 18 Jul, 2012 1 commit
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Avi Kivity authored
Signed-off-by:
Avi Kivity <avi@redhat.com> Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com>
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- 16 Jul, 2012 3 commits
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Michael S. Tsirkin authored
This reverts commit f9808b7f. After commit 'kvm: switch to apic_set_eoi_write, apic_write' the stubs are no longer needed as kvm does not look at apicdrivers anymore. Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
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Michael S. Tsirkin authored
Use apic_set_eoi_write, apic_write to avoid meedling in core apic driver data structures directly. Signed-off-by:
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Michael S. Tsirkin authored
KVM PV EOI optimization overrides eoi_write apic op with its own version. Add an API for this to avoid meddling with core x86 apic driver data structures directly. For KVM use, we don't need any guarantees about when the switch to the new op will take place, so it could in theory use this API after SMP init, but it currently doesn't, and restricting callers to early init makes it clear that it's safe as it won't race with actual APIC driver use. Signed-off-by:
Ingo Molnar <mingo@kernel.org> Signed-off-by:
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- 15 Jul, 2012 1 commit
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git://github.com/agraf/linux-2.6Avi Kivity authored
ppc queue from Alex Graf: * Prepare some of the booke code for 64 bit support * BookE: Fix ESR flag in DSI * BookE: Add rfci emulation * 'for-upstream' of git://github.com/agraf/linux-2.6: KVM: PPC: Critical interrupt emulation support KVM: PPC: e500mc: Fix tlbilx emulation for 64-bit guests KVM: PPC64: booke: Set interrupt computation mode for 64-bit host KVM: PPC: bookehv: Add ESR flag to Data Storage Interrupt KVM: PPC: bookehv64: Add support for std/ld emulation. booke: Added crit/mc exception handler for e500v2 booke/bookehv: Add host crit-watchdog exception support Signed-off-by:
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- 12 Jul, 2012 1 commit
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Mao, Junjie authored
This patch handles PCID/INVPCID for guests. Process-context identifiers (PCIDs) are a facility by which a logical processor may cache information for multiple linear-address spaces so that the processor may retain cached information when software switches to a different linear address space. Refer to section 4.10.1 in IA32 Intel Software Developer's Manual Volume 3A for details. For guests with EPT, the PCID feature is enabled and INVPCID behaves as running natively. For guests without EPT, the PCID feature is disabled and INVPCID triggers #UD. Signed-off-by:
Junjie Mao <junjie.mao@intel.com> Signed-off-by:
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- 11 Jul, 2012 18 commits
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Prarit Bhargava authored
While debugging I noticed that unlike all the other hypervisor code in the kernel, kvm does not have an entry for x86_hyper which is used in detect_hypervisor_platform() which results in a nice printk in the syslog. This is only really a stub function but it does make kvm more consistent with the other hypervisors. Signed-off-by:
Prarit Bhargava <prarit@redhat.com> Cc: Avi Kivity <avi@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Marcelo Tostatti <mtosatti@redhat.com> Cc: kvm@vger.kernel.org Signed-off-by:
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Bharat Bhushan authored
rfci instruction and CSRR0/1 registers are emulated. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by:
Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by:
Alexander Graf <agraf@suse.de>
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Mihai Caraman authored
tlbilxva emulation was using an u32 variable for guest effective address. Replace it with gva_t type to handle 64-bit guests. Signed-off-by:
Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by:
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Mihai Caraman authored
64-bit host needs to remain in 64-bit mode when an exception take place. Set interrupt computaion mode in EPCR register. Signed-off-by:
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Mihai Caraman authored
ESR register is required by Data Storage Interrupt handling code. Add the specific flag to the interrupt handler. Signed-off-by:
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Varun Sethi authored
Add support for std/ld emulation. Signed-off-by:
Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by:
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Bharat Bhushan authored
Watchdog is taken at critical exception level. So this patch is tested with host watchdog exception happening when guest is running. Signed-off-by:
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Bharat Bhushan authored
Signed-off-by:
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Xiao Guangrong authored
Document fast page fault and mmu-lock in locking.txt Signed-off-by:
Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com> Signed-off-by:
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Xiao Guangrong authored
The P bit of page fault error code is missed in this tracepoint, fix it by passing the full error code Signed-off-by:
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Xiao Guangrong authored
To see what happen on this path and help us to optimize it Signed-off-by:
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Xiao Guangrong authored
If the the present bit of page fault error code is set, it indicates the shadow page is populated on all levels, it means what we do is only modify the access bit which can be done out of mmu-lock Currently, in order to simplify the code, we only fix the page fault caused by write-protect on the fast path Signed-off-by:
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Xiao Guangrong authored
This bit indicates whether the spte can be writable on MMU, that means the corresponding gpte is writable and the corresponding gfn is not protected by shadow page protection In the later path, SPTE_MMU_WRITEABLE will indicates whether the spte can be locklessly updated Signed-off-by:
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Xiao Guangrong authored
mmu_spte_update() is the common function, we can easily audit the path Signed-off-by:
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Xiao Guangrong authored
Export the present bit of page fault error code, the later patch will use it Signed-off-by:
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Xiao Guangrong authored
Use __drop_large_spte to cleanup this function and comment spte_write_protect Signed-off-by:
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Xiao Guangrong authored
Introduce a common function to abstract spte write-protect to cleanup the code Signed-off-by:
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Xiao Guangrong authored
The reture value of __rmap_write_protect is either 1 or 0, use true/false instead of these Signed-off-by:
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- 09 Jul, 2012 16 commits
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Avi Kivity authored
Our emulation should be complete enough that we can emulate guests while they are in big real mode, or in a mode transition that is not virtualizable without unrestricted guest support. Signed-off-by: -
Avi Kivity authored
Opcode 0F 00 /3. Encountered during Windows XP secondary processor bringup. Signed-off-by: -
Avi Kivity authored
Guest software doesn't actually depend on it, but vmx will refuse us entry if we don't. Set the bit in both the cached segment and memory, just to be nice. Signed-off-by: -
Avi Kivity authored
Some operations want to modify the descriptor later on, so save the address for future use. Signed-off-by: -
Avi Kivity authored
Opcode 0F 00 /2. Used by isolinux durign the protected mode transition. Signed-off-by: -
Avi Kivity authored
Opcodes 0F C8 - 0F CF. Used by the SeaBIOS cdrom code (though not in big real mode). Signed-off-by: -
Avi Kivity authored
If instruction emulation fails, report it properly to userspace. Signed-off-by: -
Avi Kivity authored
Process the event, possibly injecting an interrupt, before continuing. Signed-off-by: -
Avi Kivity authored
Opcode C8. Only ENTER with lexical nesting depth 0 is implemented, since others are very rare. We'll fail emulation if nonzero lexical depth is used so data is not corrupted. Signed-off-by: -
Avi Kivity authored
This allows us to reuse the code without populating ctxt->src and overriding ctxt->op_bytes. Signed-off-by: -
Avi Kivity authored
Commit 2adb5ad9 removed ByteOp from MOVZX/MOVSX, replacing them by SrcMem8, but neglected to fix the dependency in the emulation code on ByteOp. This caused the instruction not to have any effect in some circumstances. Fix by replacing the check for ByteOp with the equivalent src.op_bytes == 1. Signed-off-by:
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Avi Kivity authored
Opcode 9F. Signed-off-by: -
Avi Kivity authored
If we return early from an invalid guest state emulation loop, make sure we return to it later if the guest state is still invalid. Signed-off-by: -
Avi Kivity authored
Checking EFLAGS.IF is incorrect as we might be in interrupt shadow. If that is the case, the main loop will notice that and not inject the interrupt, causing an endless loop. Fix by using vmx_interrupt_allowed() to check if we can inject an interrupt instead. Signed-off-by: -
Avi Kivity authored
Opcodes 0F 01 /0 and 0F 01 /1 Signed-off-by: -
Avi Kivity authored
We correctly default to SS when BP is used as a base in 16-bit address mode, but we don't do that for 32-bit mode. Fix by adjusting the default to SS when either ESP or EBP is used as the base register. Signed-off-by:
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