- 31 Mar, 2023 40 commits
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Tong Liu01 authored
User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of vcn and dcn Signed-off-by:
Tong Liu01 <Tong.Liu01@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Caio Novais authored
Compiling AMD GPU drivers displays a warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’ [-Wmissing-prototypes] Get rid of it by marking the function as static Signed-off-by:
Caio Novais <caionovais@usp.br> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Amber Lin authored
On GC 9.4.3, DW 41 in MQD is repurposed as compute_tg_chunk_size for cooperative dispatch. When it's a AQL queue, set compute_tg_chunk_size as 1 to spread work groups evenly among XCCs. If it's PM4 queue, unset compute_tg_chunk_size to disable cooperative mode. v3: set compute_tg_chunk_size as 1 instead of #CUs per XCC v2: set compute_tg_chunk_size as #CUs per XCC instead of total wave slots per XCC Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Sean Keely <Sean.Keely@amd.com> Signed-off-by:
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Jay Cornwall authored
v1: Check new exception bits in TRAPSTS register Remove single step exception workaround, now part of exception bits v2: GC 9.4.3 uses ttmp11 to store {1’b0, dispatch index [24:0], wave_id_in_workgroup[5:0]}, so use ttmp13 instead of ttmp11 to preserve ib_sts. (Laurent) Signed-off-by:Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
Laurent Morichetti <Laurent.Morichetti@amd.com> Reviewed-by:
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Caio Novais authored
Compiling AMD GPU drivers displays a warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c: In function ‘dml_rq_dlg_get_dlg_params’: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14: warning: variable ‘scl_enable’ set but not used [-Wunused-but-set-variable] Get rid of it by removing the variable 'scl_enable'. Signed-off-by:
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Amber Lin authored
For GC 9.4.3, disable retry as default and XNACK can be different modes per process. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Uwe Kleine-König authored
Commit 075e2099c32c ("drm/amd/display: Fix race condition in DPIA AUX transfer") was backported to stable, which I noticed because of git saying linux-6.1/.git/rebase-apply/patch:37154: space before tab in indent. while applying patch-6.1.21. While fixing the code location that issued that warning, improve in few more places. Signed-off-by:Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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Hawking Zhang authored
Add initial KFD support Convert a few structures to IP version checking (Hawking) Signed-off-by:
Elena Sakhnovitch <elena.sakhnovitch@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Aric Cyr authored
This DC version brings along: - Enable FPO optimization - Support for 6.75 GBps link rate - Fixes to underflow, black screen and more Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] Assign the correct info now that FW headers are promoted Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Anthony Koo authored
- New parameter to define extra vblank stretch required when doing FPO + Vactive - Pass in pipe index for FPO Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Peichen Huang authored
[Why] Some dock and mst monitor don't like to receive CLEAR_PAYLOAD_ID_TABLE when mst_en is set to 0. It doesn't make sense to do so in source side, either. [How] Don't send CLEAR_PAYLOAD_ID_TABLE if mst_en is 0 Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Peichen Huang <PeiChen.Huang@amd.com> Tested-by:
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Alvin Lee authored
[Description] Enable optimization for preferring FPO if it achieves a lower voltage level Reviewed-by:
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Alvin Lee authored
[Description] If transitioning from an FPO config -> FPO config, we want to keep cursor P-State force disallowed. Any other transition from FPO config -> non FPO config should unforce the cursor P-State disallow Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Artem Grishin authored
[Why] The 6.75 GBps link rate is part of the new eDP specification version 1.5 is going to be supported in the future. Since this standard is very new and there are no existing 6.75 GBps panels on the market yet, we should put a condition in the driver on enabling this feature until we can validate it with real hardware. [How] - Add boolean flag support_eDP1_5 in struct dc_debug_options. - Enable the 6.75 link rate in reduce_link_rate(...) only when the flag is true. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Artem Grishin <Artem.Grishin@amd.com> Tested-by:
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Artem Grishin authored
[Why] The latest eDP spec version 1.5 defines a new generic link rate of 6.75 Gbps/Lane, which needs to be supported in the driver. [How] Added new element to the dc_link_rate enum Reviewed-by:
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Ayush Gupta authored
[Why] Observing underflow on dcn30+ system config at 4k144hz [How] We set the UCLK hardmax on AC/DC switch if softmax is enabled and also on boot. While booting up the UCLK Hardmax is set to softmax before the init sequence and the init sequence resets the hardmax to UCLK max which enables P-state switching. Just added a conditional check to avoid setting hardmax on init. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Ayush Gupta <ayugupta@amd.com> Tested-by:
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Alvin Lee authored
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This change is in preparation to enable FPO + VActive * Use per pipe P-State force for FPO - For FPO, instead of using max watermarks value for P-State disallow, use per pipe p-state force instead - This is in preparation to enable FPO + VActive Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Qingqing Zhuo authored
As part of the FAMS work, we need code infrastructure in DC. dcn30_fpu.c changes went missing during previous upstream activity. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Taimur Hassan authored
[Why & How] Needed to get certain EDID to light up during TMDS compliance. Reviewed-by:
Taimur Hassan <Syed.Hassan@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[Why & How] w/a for dcn315 inconsistent smu clock. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Charlene Liu authored
[why] HW delta follow up Reviewed-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
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Martin Leung authored
[Why & How] when trying to fix a nullptr dereference on VMs, accidentally doubly allocated memory for the non VM case. removed the extra link_srv creation since dc_construct_ctx is called in both VM and non VM cases Also added a proper fail check for if kzalloc fails Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Leo Ma <Hanghong.Ma@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DPP Root clock optimization when combined with 4to1 MPC combine results in the screen turning black. This is because the DPPCLK is stopped during the middle of an optimize_bandwidth sequence during commit_minimal_transition without going through plane power down/power up. [How] The intent of a 0Hz DPP clock through update_clocks is to disable the DTO. This differs from the behavior of stopping the DPPCLK entirely (utilizing a 0Hz clock on some ASIC) so it's better to move this logic to reside next to plane power up/power down where we gate the HUBP/DPP DOMAIN. The new sequence should be: Power down: PG enabled -> RCO on Power up: RCO off -> PG disabled Rename power_on_plane to power_on_plane_resources to reflect the actual operation that's occurring. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Alvin Lee authored
[Descrtipion] - Driver hardcoded FCLK P-State latency was incorrect - Use the value provided by PMFW header instead Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
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Alvin Lee authored
[Description] - On high refresh rate DRR displays that support VBLANK naturally, UCLK could be idling at DPM1 instead of DPM0 since it doesn't use FPO - To achieve DPM0, enable FPO on these configs even though it can support P-State without FPO - Default disable for now, have debug option to enable Reviewed-by:
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Nicholas Kazlauskas authored
[Why] While scanning the top_pipe connections we can run into a case where the bottom pipe is still connected to a top_pipe but with a NULL plane_state. [How] Treat a NULL plane_state the same as the plane being invisible for pipe cursor disable logic. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Hawking Zhang authored
Fix backward compatibility issue to stay with the old name of xgmi_wafl node. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Tim Huang authored
If the gfx imu is poweroff when suspend, then it need to be re-enabled when resume. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Yifan Zha authored
[Why] Reset(mode1) failed as JPRG IP did not reinit under sriov. [How] Add JPEG IP block to sriov reinit function. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
Horace Chen <Horace.Chen@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Global variables do not need to be initialized to 0 or NULL and checkpatch flags this error in drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c: ERROR: do not initialise globals to NULL +char *amdgpu_disable_cu = NULL; +char *amdgpu_virtual_display = NULL; Fix this checkpatch error. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Hawking Zhang authored
Add GMC IP handling for GC 9.4.3 Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Le Ma authored
Initialize gfxhub1.2 and mmhub1.8 function calls Signed-off-by:
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Le Ma authored
Hack the mmhub 1.7 reg offset for initial support v2: squash in header switch, CG funcs (Alex) Signed-off-by:
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Hawking Zhang authored
Add mmhub v1_8_0 register offset and shift masks header files v2: update headers (Alex) Signed-off-by:
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Le Ma authored
Hack the gc 9.0 reg offset for initial support v2: squash in header switch (Alex) Signed-off-by:
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Hawking Zhang authored
Initialize various gmc sw/hw settings/configurations for GC 9.4.3. Signed-off-by:
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Hawking Zhang authored
Add gc v9_4_3 register offset and shift masks header files v2: update headers (Alex) v3: more updates (Alex) Signed-off-by:
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Hawking Zhang authored
Add osssys v4_4_2 register offset and shift masks header files v2: update headers (Alex) Signed-off-by:
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Hawking Zhang authored
Add athub v1_8_0 register offset and shift masks header files v2: update headers (Alex) Signed-off-by:
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