- 16 Jul, 2019 20 commits
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Nathan Chancellor authored
clang warns: drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:995:39: warning: implicit conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:1016:39: warning: implicit conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:1031:39: warning: implicit conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ The values are mapped one to one in vega20_get_smu_clk_index so just use the proper enums here. Fixes: 09676101 ("drm/amd/powerplay: support sysfs to get socclk, fclk, dcefclk") Link: https://github.com/ClangBuiltLinux/linux/issues/587Reviewed-by:Evan Quan <evan.quan@amd.com> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicolai Hähnle authored
Prefetch mode 0 is not supported and can lead to hangs with certain very specific code patterns. Set a sound prefetch mode for all VMIDs rather than forcing all shaders to set the prefetch mode at the beginning. Reduce code duplication a bit while we're at it. Note that the 64-bit address mode enum and the retry all enum are both 0, so the only functional change is in the INITIAL_INST_PREFETCH field. Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Kenneth Feng authored
enable fw ctf, apcc dfll and gfx ss on navi10. fw ctf: when the fw ctf is triggered, the gfx and soc power domain are shut down. fan speed is boosted to the maximum. gfx ss: hardware feature, sanity check has been done. apcc dfll: can check the scoreboard in smu fw to confirm if it's enabled. no need to do further check since the gfx hardware control the frequency once a pcc signal comes. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Hawking Zhang authored
The legacy navi10 sos binary will not carry on kdb image. the kdb_start_addr is actually the start address of sys_drv image and shouldn't be sent to psp bootloader. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Felix Kuehling authored
When starting a new mm_node, the page_offset becomes 0. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Wang Xiayang authored
The simple_strtol() function is deprecated. kstrto[l,u32]() is the correct replacement as it can properly handle overflows. This patch replaces the deprecated simple_strtol() use introduced recently. As clk is of type uint32_t, we are safe to use kstrtou32(). It is also safe to return zero on string parsing error, similar to the case of returning zero if buf is empty in parse_clk(). Fixes: bb5a2bdf ("drm/amdgpu: support dpm level modification under virtualization v3") Signed-off-by:
Wang Xiayang <xywang.sjtu@sjtu.edu.cn> Signed-off-by:
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Fuqian Huang authored
kzalloc has already zeroed the memory during the allocation. So memset is unneeded. Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Signed-off-by:
Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by:
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Arnd Bergmann authored
It is annoying to have #warnings that trigger in randconfig builds like drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15." drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi." Remove these and rely on the users to turn these on. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Kent Russell authored
The perf counter for Vega20 is 108, instead of 104 which it was on all previous GPUs, so add a check to use the appropriate value. Signed-off-by:
Kent Russell <kent.russell@amd.com> Acked-by:
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Tom St Denis authored
The ability to select GFX GRBM me/pipe/queue/vmid was missing from the gfx10 driver. This patch adds it. Used by the debugfs register interface to select GFX resources when read/writing registers. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Add 5 bits to the offset for SRBM selection to handle VMIDs. Also update the select_me_pipe_q() callback to also select VMID. Signed-off-by:
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Emil Velikov authored
Currently the AMDGPU_CTX_PRIORITY_* defines are used in both drm_amdgpu_ctx_in::priority and drm_amdgpu_sched_in::priority. Extend the comment to mention the CAP_SYS_NICE or DRM_MASTER requirement is only applicable with the former. Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Kevin Wang authored
v2: change function name to smu_clk_dpm_is_enabled. add this helper function to check dpm clk feature is enabled. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Kevin Wang authored
the save dpm level should be save previous dpm profile level, should not modified by get dpm level function. eg: default auto 1. auto -> standard ==> dpm_level = standard, save_dpm = auto. 2. standard -> auto ==> dpm_level = auto, save_dpm = standard. Signed-off-by:
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Kevin Wang authored
the unforce_dpm_levels doesn't need to check feature enablement. because the smu_get_dpm_freq_range function has check feature logic. Signed-off-by:
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Kevin Wang authored
1. the standard dpm is not support before. 2. use auto profile to adapt standard profile. Signed-off-by:
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Kevin Wang authored
1.miss socclk profile support when bringup. 2.add feature check for socclk. Signed-off-by:
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Felix Kuehling authored
Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by:
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Arnd Bergmann authored
clang complains that 'false' is a not a pointer: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:2428:10: error: expression which evaluates to zero treated as a null pointer constant of type 'struct pipe_ctx *' [-Werror,-Wnon-literal-null-conversion] return false; Changing it to 'NULL' looks like the right thing that will shut up the warning and make it easier to read, while not changing behavior. Fixes: 7ed4e635 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Reviewed-by: -
Arnd Bergmann authored
As previously fixed for dml in commit 4769278e ("amdgpu/dc/dml: Support clang option for stack alignment") and calcs in commit cc32ad8f ("amdgpu/dc/calcs: Support clang option for stack alignment"), dcn20 uses an option that is not available with clang: clang: error: unknown argument: '-mpreferred-stack-boundary=4' scripts/Makefile.build:281: recipe for target 'drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.o' failed Use the same trick that we have in the other two files. Fixes: 7ed4e635 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by:
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- 12 Jul, 2019 5 commits
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Kevin Wang authored
add pstate mclk(uclk) support. Signed-off-by:
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Kevin Wang authored
in the smu module, use the smu_xxxclk type to identify the CLK type use SMU_SCLK, SMU_MCLK to replace PP_SCLK, PP_MCLK. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Hawking Zhang authored
Starting from navi10, driver should send Key Database Load command to bootloader before loading sys_drv and sos Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
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Hawking Zhang authored
The command will be sent to psp bootloader from driver to ask psp bootloader to exerise tOS, sys_drv and kdb loading Signed-off-by:
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Paul Menzel authored
As the clock is already logged, also log the voltage. Signed-off-by:
Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by:
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- 11 Jul, 2019 8 commits
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Nicholas Kazlauskas authored
[Why] The drm_audio_component can be used to give pin ELD notifications directly to the sound driver. This fixes audio endpoints disappearing due to missing unsolicited notifications. [How] Send the notification via the audio component whenever we enable or disable audio state on a stream. This matches what i915 does with their drm_audio_component and what Takashi Iwai's proposed hack for radeon/amdpgu did. This is a bit delayed in when the notification actually occurs, however. We wait until after all the programming is complete rather than sending the notification mid sequence. Particular care is needed for the get ELD callback since it can happen outside the locking and fencing DRM does for atomic commits. Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] In order to give pin notifications to the sound driver from DM we need to know whether audio is enabled on a stream and what pin it's using from DC. [How] Expose the instance via stream status if it's a mapped resource for the stream. It will be -1 if there's no audio mapped. Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Eric Huang authored
The cp hang occurs in OCL conformance test only on supermicro platform which has 40 cores and the test generates 40 threads. The root cause is race condition in non-protected flags. The fix is to add flags of is_evicted and is_active(init_mqd()) into protected area. Signed-off-by:
Eric Huang <JinhuiEric.Huang@amd.com> Reviewed-by:
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Alex Deucher authored
Use the IP discovery table rather than hardcoding the settings in the driver. Reviewed-by:
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tiancyin authored
ID of DCE_HWIP from vbios is DMU_HWID, mismatch cause null pointer crash in navi10 modprobe. Reviewed-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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Kenneth Feng authored
when we set profile_peak to sysfs:power_dpm_force_performance_level, we gets the wrong socclk level and mclk level.this patch fix this issue. Signed-off-by:
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Evan Quan authored
This is expected to fix some mode1 reset failures. And this affects SMU part only as the timeout setting for other parts is controlled by a different macro. Signed-off-by:
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Felix Kuehling authored
With mm_nodes larger than 4GB, byte_count in amdgpu_fill_buffer would overflow. Signed-off-by:
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- 09 Jul, 2019 5 commits
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Alex Deucher authored
We need to serialize access to the psp ring if there are multiple callers at runtime. Reviewed-by:
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Alex Deucher authored
Query the metrics table for the current uclk activity. Reviewed-by:
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Alex Deucher authored
It's only available on navi and newer. Reviewed-by:
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Alex Deucher authored
New parameters added for navi lack documentation. Reviewed-by:
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Marek Olšák authored
This RELEASE_MEM use has the Release semantic, which means we should write back but not invalidate. Invalidations only make sense with the Acquire semantic (ACQUIRE_MEM), or when RELEASE_MEM is used to do the combined Acquire-Release semantic, which is a barrier, not a fence. The undesirable side effect of doing invalidations for the Release semantic is that it invalidates caches while shaders are running, because the Release can execute in the middle of the next IB. UMDs should use ACQUIRE_MEM at the beginning of IBs. Doing cache invalidations for a fence (like in this case) doesn't do anything for correctness. Signed-off-by:
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- 08 Jul, 2019 2 commits
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Arnd Bergmann authored
On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6a ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e5 ("drm/amd/display: update calculated bounding box logic for NV") Acked-by:
Slava Abramov <slava.abramov@amd.com> Tested-by:
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Alex Deucher authored
Split it between navi10 and newer and everything before navi10. Reviewed-by:
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