1. 23 Jan, 2020 2 commits
    • Georgi Djakov's avatar
      clk: qcom: gcc-sdm845: Add missing flag to votable GDSCs · d8a82587
      Georgi Djakov authored
      commit 5e82548e upstream.
      
      On sdm845 devices, during boot we see the following warnings (unless we
      have added 'pd_ignore_unused' to the kernel command line):
      	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc status stuck at 'on'
      	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc status stuck at 'on'
      	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_tbu2_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_tbu1_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc status stuck at 'on'
      
      As the name of these GDSCs suggests, they are "votable" and in downstream
      DT, they all have the property "qcom,no-status-check-on-disable", which
      means that we should not poll the status bit when we disable them.
      
      Luckily the VOTABLE flag already exists and it does exactly what we need,
      so let's make use of it to make the warnings disappear.
      
      Fixes: 06391edd ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
      Reported-by: default avatarRob Clark <robdclark@gmail.com>
      Signed-off-by: default avatarGeorgi Djakov <georgi.djakov@linaro.org>
      Link: https://lkml.kernel.org/r/20191126153437.11808-1-georgi.djakov@linaro.orgTested-by: default avatarRob Clark <robdclark@gmail.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      d8a82587
    • Martin Blumenstingl's avatar
      ARM: dts: meson8: fix the size of the PMU registers · 3adc34ef
      Martin Blumenstingl authored
      commit 46c9585e upstream.
      
      The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
      size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
      is similar but not identical.
      
      Meson8 and Meson8b have the following registers in common (starting at
      AOBUS + 0xe0):
        #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
        #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
        #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
        #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
      
      Meson8b additionally has these three registers:
        #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
        #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
        #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
      
      Thus we can assume that the register size of the PMU IP blocks is
      identical on both SoCs (and Meson8 just contains some reserved registers
      in that area) because the CEC registers start right after the PMU
      (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
      
      The upcoming power domain driver will need to read and write the
      AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
      size is needed for that driver to work.
      
      Fixes: 4a5a2711 ("ARM: dts: meson8: add support for booting the secondary CPU cores")
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      3adc34ef
  2. 17 Jan, 2020 38 commits