- 16 Dec, 2021 1 commit
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Vinod Koul authored
Document the compatible string for USB phy found in Qualcomm SM8450 SoC Signed-off-by:
Vinod Koul <vkoul@kernel.org> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213131450.535775-1-vkoul@kernel.orgSigned-off-by:
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- 15 Dec, 2021 1 commit
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Vinod Koul authored
kernel test robot complains about missing FIELD_PREP, so include bitfield.h for that drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:37: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] Reported-by:
kernel test robot <lkp@intel.com> Fixes: 1aa97b00 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Link: https://lore.kernel.org/r/20211215060834.921617-1-vkoul@kernel.orgSigned-off-by:
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- 14 Dec, 2021 8 commits
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Richard Zhu authored
Add the standalone i.MX8 PCIe PHY driver. Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
Tim Harvey <tharvey@gateworks.com> Tested-by:
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Richard Zhu authored
Add dt-binding for the standalone i.MX8 PCIe PHY driver. Signed-off-by:
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Richard Zhu authored
Add binding for reference clock PAD modes of the i.MX8 PCIe PHY. Signed-off-by:
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Colin Ian King authored
Variable delay is being assigned to zero and the code falls through to the next case in a switch statement that returns out of the function. The variable is never read in this scenario and so the assignment is redundant and can be removed. Cleans up scan-build static analysis warning: drivers/phy/rockchip/phy-rockchip-inno-usb2.c:753:3: warning: Value stored to 'delay' is never read [deadcode.DeadStores] Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20211211180054.525368-1-colin.i.king@gmail.comSigned-off-by:
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Horatiu Vultur authored
Remove the set_speed function and allow the driver to figure out the speed at which needs to configure the serdes based on the interface type. Fixes: 30552490 ("phy: Add lan966x ethernet serdes PHY driver") Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20211211214717.1284306-1-horatiu.vultur@microchip.comSigned-off-by:
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Miaoqian Lin authored
Use IS_ERR_OR_NULL() to make the code cleaner. Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20211212142226.23674-1-linmq006@gmail.comSigned-off-by:
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Luca Weiss authored
Add devicetree compatible for the usb phy on SM6350 SoC. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Acked-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20211213082614.22651-5-luca.weiss@fairphone.comSigned-off-by:
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Miaoqian Lin authored
callers of tegra_xusb_find_port_node() function only do NULL checking for the return value. return NULL instead of ERR_PTR(-ENOMEM) to keep consistent. Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20211213020507.1458-1-linmq006@gmail.comSigned-off-by:
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- 09 Dec, 2021 1 commit
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Guo Zhengkui authored
Use struct_size() to get the accurate size of `clk_hw_onecell_data` with a variable size array, instead of sizeof(data) to get the size of a pointer. Suggested-by:
Guo Zhengkui <guozhengkui@vivo.com> Fixes: f199223c ("phy: qcom: Introduce new eDP PHY driver") Reviewed-by:
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- 07 Dec, 2021 3 commits
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Vinod Koul authored
SM8450 UFS seems to use same sequence as SM8350, so reuse the sequence from SM8450. Add the new clock list for this phy and the new compatible Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Martin K. Petersen <martin.petersen@oracle.com> Link: https://lore.kernel.org/r/20211201074456.3969849-4-vkoul@kernel.orgSigned-off-by:
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Vinod Koul authored
Document the UFS phy compatible for QMP UFS phy found in SM8450 SoC. Signed-off-by:
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Vinod Koul authored
Document "qcom,sm8450-ufshc" compatible string. "qcom,sm8450-ufshc" is for UFS HC found in SM8450 SoC. Signed-off-by:
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- 02 Dec, 2021 2 commits
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Horatiu Vultur authored
Currently the driver is supporting only the interfaces QSGMII, SGMII, RGMII and GMII. This patch extend the supported interfaces with 1000BASE-X and 2500BASE-X. Signed-off-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20211130101015.164916-1-horatiu.vultur@microchip.comSigned-off-by:
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Zou Wei authored
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1637822289-24534-1-git-send-email-zou_wei@huawei.comSigned-off-by:
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- 26 Nov, 2021 1 commit
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Fabrice Gasnier authored
Change stm32-usbphyc driver to use dev_err_probe(), to benefit of devices_deferred debugfs in case of probe deferral. Signed-off-by:
Fabrice Gasnier <fabrice.gasnier@foss.st.com> Reviewed-by:
Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/1635172265-26219-1-git-send-email-fabrice.gasnier@foss.st.comSigned-off-by:
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- 25 Nov, 2021 1 commit
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Rafał Miłecki authored
Improve message & use dev_err_probe() helper which prints actual error (helpful for debugging) and deals with -EPROBE_DEFER. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211123221521.25323-1-zajec5@gmail.comSigned-off-by:
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- 23 Nov, 2021 21 commits
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Rashmi A authored
Add support of eMMC PHY for Intel Thunder Bay SoC, uses the Arasan eMMC phy Signed-off-by:
Rashmi A <rashmi.a@intel.com> Reviewed-by:
Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20211027115516.4475-5-rashmi.a@intel.comSigned-off-by:
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Rashmi A authored
Binding description for Intel Thunder Bay eMMC PHY. Added the newly introduced files into MAINTAINERS file-list Signed-off-by:
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Horatiu Vultur authored
Add the Microchip lan966x ethernet serdes PHY driver for interfaces available in the lan966x SoC. Signed-off-by:
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Horatiu Vultur authored
Lan966x has: 2 integrated PHYs, 3 SerDes and 2 RGMII interfaces. Which requires to be muxed based on the HW representation. So add constants for each interface to be able to distinguish them. Reviewed-by:
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Horatiu Vultur authored
Document the lan966x ethernet serdes phy driver bindings. Reviewed-by:
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Aswath Govindraju authored
In some cases the standby/enable gpio can be pulled low/high and would not be connected to a gpio. The current driver implementation will return an error in these cases. Therefore, make devm_gpiod_get optional. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Acked-by:
Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20211102112120.23637-1-a-govindraju@ti.comSigned-off-by:
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Yang Guang authored
Use the macro 'swap()' defined in 'include/linux/minmax.h' to avoid opencoding it. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Yang Guang <yang.guang5@zte.com.cn> Link: https://lore.kernel.org/r/20211104065233.1833499-1-yang.guang5@zte.com.cnSigned-off-by:
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Kunihiko Hayashi authored
Add support for PHY interface built into ahci controller implemented in UniPhier Pro4 SoC. Pro4 SoC distinguishes it from other SoCs as "legacy" SoC, which has GIO clock line. And Pro4 AHCI-PHY needs to control additional reset lines ("pm", "tx", and "rx"). Signed-off-by:Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1635503947-18250-9-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Kunihiko Hayashi authored
Update AHCI-PHY binding document for UniPhier Pro4 SoC. Add a compatible string, clock and reset lines for the SoC to the document. Pro4 AHCI-PHY needs to control additional GIO clock line and reset lines ("pm", "tx", and "rx"). Signed-off-by: -
Kunihiko Hayashi authored
NX1 SoC supports 2 lanes and has dual-phy. Should set appropriate configuration values to both PHY registers. Signed-off-by:
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Kunihiko Hayashi authored
Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue. Signed-off-by:
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Kunihiko Hayashi authored
Add basic support for UniPhier NX1 SoC. This includes a compatible string, SoC-dependent data, and a function that set to 2-lane mode. Signed-off-by:
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Kunihiko Hayashi authored
Update PCIe-PHY binding document for UniPhier NX1 SoC. Add a compatible string for the SoC to the document. Signed-off-by:
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Kunihiko Hayashi authored
Add basic support for UniPhier NX1 SoC. This includes a compatible string and the same SoC-dependent data as LD20/PXs3 SoCs. Signed-off-by:
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Kunihiko Hayashi authored
Update USB3-PHY binding document for UniPhier NX1 SoC. Add SS-PHY and HS-PHY compatible strings for the SoC to the document. Signed-off-by:
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David Heidelberg authored
Convert Tegra194 P2U binding to the YAML format. Signed-off-by:
David Heidelberg <david@ixit.cz> Reviewed-by:
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Martin Blumenstingl authored
Amlogic Meson8/8b/8m2 have a built-in HDMI PHY in the HHI register region. Unfortunately only few register bits are documented. For HHI_HDMI_PHY_CNTL0 the magic numbers are taken from the 3.10 vendor kernel. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20211020195107.1564533-3-martin.blumenstingl@googlemail.comSigned-off-by:
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Martin Blumenstingl authored
Amlogic Meson8, Meson8b and Meson8m2 all include an identical (or at least very similar) HDMI TX PHY. The PHY registers are part of the HHI register area. Signed-off-by:
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Bjorn Andersson authored
Many recent Qualcomm platforms comes with native DP and eDP support. This consists of a controller in the MDSS and a QMP-like PHY. While similar to the well known QMP block, the eDP PHY only has TX lanes and the programming sequences are slightly different. Rather than continuing the trend of parameterize the QMP driver to pieces, this introduces the support as a new driver. The registration of link and pixel clocks are borrowed from the QMP driver. The non-DP link frequencies are omitted for now. The eDP PHY is very similar to the dedicated (non-USB) DP PHY, but only the prior is supported for now. Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20211103234410.1352424-2-bjorn.andersson@linaro.orgSigned-off-by:
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Bjorn Andersson authored
Introduce a binding for the eDP PHY hardware block found in several different Qualcomm platforms. Signed-off-by:
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Rafał Miłecki authored
Updated DT binding maps just a PHY's register space instead of the whole DMU block. Accessing a common CRU reg is handled using syscon & regmap. The old binding has been deprecated and remains supported as a fallback method. Signed-off-by:
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- 14 Nov, 2021 1 commit
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Linus Torvalds authored
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