- duty cycle setting support on qcom clks
 - qcom MDM9607 GCC
 - qcom sc8180x display clks
 - qcom SM6125 GCC
 - Add TI am33xx spread spectrum clock support

* clk-qcom: (22 commits)
  clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare
  clk: qcom: Add camera clock controller driver for SM8250
  dt-bindings: clock: add QCOM SM8250 camera clock bindings
  clk: qcom: clk-alpha-pll: add support for zonda pll
  clk/qcom: Remove unused variables
  clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocks
  clk: qcom: gcc: Add support for Global Clock controller found on MSM8226
  dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings
  clk: qcom: Add SM6125 (TRINKET) GCC driver
  dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver
  clk: qcom: gcc: Add support for a new frequency for SC7280
  clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLK
  dt-bindings: clock: qcom: rpmcc: Document MSM8226 compatible
  clk: qcom: dispcc-sm8250: Add EDP clocks
  clk: qcom: dispcc-sm8250: Add sc8180x support
  clk: qcom: smd-rpm: De-duplicate identical entries
  clk: qcom: smd-rpm: Switch to parent_data
  clk: qcom: Add MDM9607 GCC driver
  dt-bindings: clock: Add MDM9607 GCC clock bindings
  clk: qcom: cleanup some dev_err_probe() calls
  ...

* clk-versatile:
  clk: versatile: Depend on HAS_IOMEM
  clk: versatile: remove dependency on ARCH_*

* clk-renesas: (22 commits)
  clk: renesas: Add support for R9A07G044 SoC
  clk: renesas: Add CPG core wrapper for RZ/G2L SoC
  dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
  clk: renesas: r8a77995: Add ZA2 clock
  clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
  clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
  clk: renesas: r9a06g032: Switch to .determine_rate()
  clk: renesas: div6: Implement range checking
  clk: renesas: div6: Consider all parents for requested rate
  clk: renesas: div6: Switch to .determine_rate()
  clk: renesas: div6: Simplify src mask handling
  clk: renesas: div6: Use clamp() instead of clamp_t()
  clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()
  clk: renesas: r8a779a0: Add ISPCS clocks
  clk: renesas: rcar-gen3: Add boost support to Z clocks
  clk: renesas: rcar-gen3: Add custom clock for PLLs
  clk: renesas: rcar-gen3: Increase Z clock accuracy
  clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/
  clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()
  ...

* clk-sifive:
  clk: analogbits: fix doc warning in wrpll-cln28hpc.c
  clk: sifive: Fix kernel-doc

* clk-ti:
  drivers: ti: remove redundant error message in adpll.c
  clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk
  dt-bindings: clock: ehrpwm: Add support for AM64 specific compatible
  clk: ti: add am33xx/am43xx spread spectrum clock support
  ARM: dts: am43xx-clocks: add spread spectrum support
  ARM: dts: am33xx-clocks: add spread spectrum support
  dt-bindings: ti: dpll: add spread spectrum support
  clk: ti: fix typo in routine description

There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Yu Jiahua <yujiahua1@huawei.com>
Link: https://lore.kernel.org/r/20210616034826.37276-1-yujiahua1@huawei.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Caught this when looking at alpha-pll code. Untested but it is clear that
this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL.

Fixes: 691865ba ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.caSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Add support for the camera clock controller found on SM8250.

Based on the downstream driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Link: https://lore.kernel.org/r/20210609022051.2171-4-jonathan@marek.ca
[sboyd@kernel.org: Add UL to avoid decimal problems]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add device tree bindings for camera clock controller for
Qualcomm Technology Inc's SM8250 SoC.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210609022051.2171-3-jonathan@marek.caReviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Ported over from the downstream driver. Will be used by SM8250 CAMCC.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210609022051.2171-2-jonathan@marek.caSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Fix gcc '-Wunused-const-variable' warnings:

  drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1'
    defined but not used [-Wunused-const-variable=]
  drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map'
    defined but not used [-Wunused-const-variable=]
  drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined
    but not used [-Wunused-const-variable=]
  drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map'
    defined but not used [-Wunused-const-variable=]

Let's remove them.
Signed-off-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/r/20210609061848.87415-1-pulehui@huawei.comReported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add compatible for rpm smd clocks, PMIC and bus clocks which are required
on MSM8226 for clients to vote on.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210605104040.12960-1-bartosz.dudziak@snejp.plSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies
which are different in this older chip. Register all the clocks to the
framework for the clients to be able to request for them.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210418122909.71434-3-bartosz.dudziak@snejp.plSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Add compatible device strings and the include files for the MSM8226 GCC.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210418122909.71434-2-bartosz.dudziak@snejp.plAcked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add the clocks supported in global clock controller, which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20210605121040.282053-2-martin.botka@somainline.orgReviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[sboyd@kernel.org: Mark gcc_sm6125_hws array static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Document the newly added SM6125 GCC driver.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20210605121040.282053-1-martin.botka@somainline.orgReviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

There is a requirement to support 52MHz for qup clocks for bluetooth
usecase, thus update the frequency table to support the frequency.

Fixes: a3cc0921 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1624449471-9984-1-git-send-email-tdas@codeaurora.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

AM64 has 9 instances of EPWM modules. And each instance has a clk to
Timer-Base sub-module that can be controlled by Control module. Update
the driver with all the 9 instance of clocks associated to
ti,am64-epwm-tbclk.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210528045743.16537-3-lokeshvutla@ti.comReviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Introduce AM64 specific compatible for epwm time-base sub-module clock.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210528045743.16537-2-lokeshvutla@ti.comAcked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'renesas-clk-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the new RZ/G2L SoC

* tag 'renesas-clk-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Add support for R9A07G044 SoC
  clk: renesas: Add CPG core wrapper for RZ/G2L SoC
  dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions

Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.

Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@renesas.com>.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Renesas RZ/G2L DT Binding Definitions

Clock definitions for the Renesas RZ/G2L (R9A07G044) SoC, shared by
driver and DT source files.

Add CPG core wrapper for RZ/G2L family.

Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@renesas.com>.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210609153230.6967-8-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs, as listed in Table 8.3 ("Clock List")
of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-7-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for
the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for
DDR, PER, and CORE PLLs.

Calculating the required values and setting the registers accordingly
was taken from the set_mpu_spreadspectrum routine contained in the
arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.

In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
SSC enabled, the reference manual explains that there is a restriction
of range of M values. Since the omap2_dpll_round_rate routine attempts
to select the minimum possible N, the value of M obtained is not
guaranteed to be within the range required. With the new "ti,min-div"
parameter it is possible to increase N and consequently M to satisfy the
constraint imposed by SSC.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.itSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruhl7x RM, SSC is supported only for LCD
and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and
PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field
in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE,
MPU, DDR, PER, DISP, EXTDEV).
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210606202253.31649-5-dariobin@libero.itSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for LCD
and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and
CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the
CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR,
PER, DISP).
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.itSigned-off-by: Stephen Boyd <sboyd@kernel.org>

DT bindings for enabling and adjusting spread spectrum clocking have
been added.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210606202253.31649-3-dariobin@libero.itSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210606202253.31649-2-dariobin@libero.itSigned-off-by: Stephen Boyd <sboyd@kernel.org>

During my big cleanup I managed to assign an AO clock to its
non-AO binding. Fix this.
Reported-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210606192657.51037-1-konrad.dybcio@somainline.org
Fixes: a0384ecf ("clk: qcom: smd-rpm: De-duplicate identical entries")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

kbuild robot reports that s390 fails to build this driver with
COMPILE_TEST. Let's depend on HAS_IOMEM so that s390 doesn't try to
build it.

Cc: Lee Jones <lee.jones@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reported-by: kernel test robot <lkp@intel.com>
Fixes: 419b3ab6 ("clk: versatile: remove dependency on ARCH_*")
Link: https://lore.kernel.org/r/20210604192321.2594519-1-sboyd@kernel.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Add the dt-binding for the RPM Clock Controller on the MSM8226 SoC.
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
Link: https://lore.kernel.org/r/20210502122027.9351-4-bartosz.dudziak@snejp.plAcked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.orgAcked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

The display clock controller in SC8180x is reused from SM8150, so add
the necessary compatible and wire up the driver to enable this.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.orgAcked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

It makes negative sense to keep repeating the same definitions
over and over and over and over again, just with changed names..

De-duplicate to make for a drastically smaller file size. This makes the
object file size 55% smaller according to bloat-o-meter:

 Total: Before=70713, After=31353, chg -55.66%
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210524225456.398817-2-konrad.dybcio@somainline.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Switch to parent_data and with that fix the longstanding issue where
if there wasn't a clock precisely named "xo_board", rpmcc would not play
along well. This started to show lately when "xo_board" was being changed to
"xo-board" so as to align with DTS naming spec.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210524225456.398817-1-konrad.dybcio@somainline.orgSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Add Global Clock Controller (GCC) support for MDM9607 SoC.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210313020310.386152-2-konrad.dybcio@somainline.org
[sboyd@kernel.org: Drop clk.h include]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Add device tree bindings for global clock controller on MDM9607 SoC.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210313020310.386152-1-konrad.dybcio@somainline.orgAcked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Fix the following make W=1 warning:

  drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting prototype for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20210601114154.3163327-1-yangyingliang@huawei.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

Fix function name in sifive-prci.c kernel-doc comment
to remove a warning.

drivers/clk/sifive/sifive-prci.c:573: warning: expecting prototype for
sifive_prci_init(). Prototype was for sifive_prci_probe() instead
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1621851730-32287-1-git-send-email-yang.lee@linux.alibaba.comReviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'renesas-clk-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for CPU core clock boost modes on R-Car Gen3
 - Add ISPCS (Image Signal Processor) clocks on R-Car V3U
 - Switch SH/R-Mobile and R-Car "DIV6" clocks to .determine_rate()
   and improve support for multiple parents
 - Switch RZ/N1 divider clocks to .determine_rate()
 - Add ZA2 (Audio Clock Generator) clock on R-Car D3
 - Minor fixes and improvements

* tag 'renesas-clk-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a77995: Add ZA2 clock
  clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
  clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
  clk: renesas: r9a06g032: Switch to .determine_rate()
  clk: renesas: div6: Implement range checking
  clk: renesas: div6: Consider all parents for requested rate
  clk: renesas: div6: Switch to .determine_rate()
  clk: renesas: div6: Simplify src mask handling
  clk: renesas: div6: Use clamp() instead of clamp_t()
  clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()
  clk: renesas: r8a779a0: Add ISPCS clocks
  clk: renesas: rcar-gen3: Add boost support to Z clocks
  clk: renesas: rcar-gen3: Add custom clock for PLLs
  clk: renesas: rcar-gen3: Increase Z clock accuracy
  clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/
  clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()
  clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32
  clk: renesas: rcar-gen3: Update Z clock rate formula in comments

It is now possible to build a modular kernel for vexpress by
not setting CONFIG_ARCH_VEXPRESS=y and instead setting =m on the
drivers that it normally implies. This is with the exception of
CLK_VEXPRESS_OSC which is currently hidden behind a dependency on
one of several ARCH_* variables. Remove that dependency so that
CLK_VEXPRESS_OSC may be enabled without it.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Link: https://linux-review.googlesource.com/id/I435a21e2e5f6187db54f4ef2079b60028ab2ea69Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210520161702.3746174-1-lee.jones@linaro.orgReviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

The dev_err_probe() function prints an error message if the error
code is not -EPROBE_DEFER.  If we know the error code in is -ENODEV
then there is no reason to check.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/YJotlJBJ1CVAgvMT@mwandaSigned-off-by: Stephen Boyd <sboyd@kernel.org>