- 12 Jul, 2023 1 commit
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Yang Wang authored
the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..). it is necessary to hold this lock to avoiding data tampering during the i2c read operation. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 07 Jul, 2023 3 commits
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2023-07-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * panel: Fix mode on Starry-ili9882t Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230706112203.GA30555@linux-uq9g
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2023-07-06' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Fix BDW PSR AUX CH data register offsets [psr] (Ville Syrjälä) - Use mock device info for creating mock device (Jani Nikula) Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-fixes-6.5-2023-06-30-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-fixes-6.5-2023-06-30-1: amdgpu: - Misc cleanups - GFX 9.4.3 fixes - DEBUGFS build fix - Fix LPDDR5 reporting - ASPM fixes - DCN 3.1.4 fixes - DP MST fixes - DCN 3.2.x fixes - Display PSR TCON fixes - SMU 13.x fixes - RAS fixes - Vega12/20 SMU fixes - PSP flashing cleanup - GFX9 MCBP fixes - SR-IOV fixes - GPUVM clear mappings fix for always valid BOs - Add FAMS quirk for problematic monitor - Fix possible UAF - Better handle monentary temperature fluctuations - SDMA 4.4.2 fixes - Fencing fix Signed-off-by:
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- 06 Jul, 2023 2 commits
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2023-06-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Allow DC states along with PW2 only for PWB functionality [adlp+] (Imre Deak) - Fix SSC selection for MPLLA [mtl] (Radhakrishna Sripada) - Use hw.adjusted mode when calculating io/fast wake times [psr] (Jouni Högander) - Apply min softlimit correctly [guc/slpc] (Vinay Belgaumkar) - Assign correct hdcp content type [hdcp] (Suraj Kandpal) - Add missing forward declarations/includes to display power headers (Imre Deak) Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2023-06-29' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * fbdev: Fix module infos on sparc Signed-off-by:
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- 04 Jul, 2023 2 commits
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Jani Nikula authored
Instead of modifying the device info on the fly, use static const mock device info. It's not okay to modify device info at runtime; we've added separate runtime info for info that needs to be modified at runtime. We've added safeguards to device info to prevent it from being modified, but commit 5e352e32 ("drm/i915: preparation for using PAT index") just cast the const away and modified it anyway. This prevents device info from being moved to rodata. Fixes: 5e352e32 ("drm/i915: preparation for using PAT index") Suggested-by:
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b0db62045a96a3fd4cf123685da88cc777f9b485.1687878757.git.jani.nikula@intel.com (cherry picked from commit ecc7a3ce) Signed-off-by:
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Ville Syrjälä authored
The multiplication got replaced by an addition in some cleanup. This means we never write the correct data to some of the BDW PSR data registers and thus we fail to actually wake up the panel from PSR. Fixes: 4ab4fa10 ("drm/i915/psr: Make PSR registers relative to transcoders") Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-3-ville.syrjala@linux.intel.comReviewed-by:
Jouni Högander <jouni.hogander@intel.com> (cherry picked from commit 460dc4ba) Signed-off-by:
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- 30 Jun, 2023 32 commits
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shanzhulig authored
fence Decrements the reference count before exiting. Avoid Race Vulnerabilities for fence use-after-free. v2 (chk): actually fix the use after free and not just move it. Signed-off-by:
shanzhulig <shanzhulig@gmail.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Evan Quan authored
An intentional delay is added on soft ctf triggered. Then there will be a double check for the GPU temperature before taking further action. This can avoid unintended shutdown due to temperature momentary fluctuation. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Preparation for coming optimization which eliminates the influence of GPU temperature momentary fluctuation. Signed-off-by:
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Aric Cyr authored
This version brings along the following: - Improve debugging mechanism for Gaming FAMS - Add monitor specific edid quirks - Fixes for Phantom pipe - Fixes for Shapper LUT - Clean up asserts Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - A full update is required if the number of planes for a given stream changes - The new fast update path only checked for stream and plane updates, but there could be a plane addition or removal without one of the stream and plane updates triggering a full update - Add an explicit check for number of planes changing for a full update Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Gianna Binder authored
[WHY] To enable FAMS even during gaming sessions. [HOW] By leveraging a new dc.debug parameter. Reviewed-by:
Felipe Clark <felipe.clark@amd.com> Acked-by:
Gianna Binder <gianna.binder@amd.com> Tested-by:
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Aurabindo Pillai authored
Disable FAMS on a Samsung Odyssey G9 monitor. Experiments show that this monitor does not work well under some use cases, and is likely implementation specific bug on the monitor's firmware. Cc: stable@vger.kernel.org Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Previous implementation didn't consider multiple surfaces in a flip - Loop through each surface in each flip to ensure the update path is correct Reviewed-by:
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Austin Zheng authored
[Why] K1 and K2 not being setting properly when subVP is active. [How] Have phantom pipes use the same programing as the main pipes without checking the paired stream Cc: stable@vger.kernel.org Tested-by:
Austin Zheng <austin.zheng@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - We want to limit the new fast update path to address and gamma updates only. - Add a check in dc_update_planes_and_stream to only take the new fast update path if we only have the specific fast updates defined. Tested-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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Harry Wentland authored
The shaper LUT requires a 10-bit value of the delta between segments. We were using dc_fixpt_clamp_u0d10() to do that but it doesn't do what we want it to do. It will preserve 10-bit precision after the decimal point, but that's not quite what we want. We want 14-bit precision and discard the 4 most-significant bytes. To do that we'll do dc_fixpt_clamp_u0d14() & 0x3ff instead. Tested-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Lijo Lazar authored
When PSP block is not present, use direct programming. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Mangesh Gadre <Mangesh.Gadre@amd.com> Tested-by:
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Melissa Wen authored
If shaper and 3D LUT data updates, lut_3d bit in update_flag is updated and we need to call set_input_transfer_func to program DPP shaper and 3D LUTs. Small cleanup of code style in the related if-condition. Tested-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Hersen Wu authored
This change causes regression when eDP and external display in mirror mode. When external display supports low resolution than eDP, use eDP timing to driver external display may cause corruption on external display. This reverts commit e749dd10. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2655Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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James Zhu authored
To save render node resoure, share drm device setting for pci amdgpu device with 1st XCP partition device. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Lijo Lazar authored
Expose unique id of GFX v9.4.3 ASICs as device attribute. Signed-off-by:
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Lijo Lazar authored
on APUs with GFX v9.4.3 Signed-off-by:
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Emily Deng authored
Need to unpause dpg first, or it will hit follow error during stop dpg: "[drm] Register(1) [regUVD_POWER_STATUS] failed to reach value 0x00000001 != 0x00000000n" Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Le Ma authored
Handled in earlier phase Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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YiPeng Chai authored
Fatal error occurs in ras poison mode, mode1 reset is used to recover gpu. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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Alex Deucher authored
It's required for high priority queues. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2535Reviewed-and-tested-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
So we can selectively enable it on certain devices. No intended functional change. Reviewed-and-tested-by:
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Mario Limonciello authored
PSP functions are already set by psp_early_init() so initializing them a second time is unnecessary. No intended functional changes. Signed-off-by:
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Mario Limonciello authored
This reverts commit 072030b1. This is no longer necessary when using newer DMUB F/W. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Mario Limonciello authored
The same parade TCON issue can potentially happen on Phoenix, and the same PSR resilience changes have been ported into the DMUB firmware. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Signed-off-by:
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Mario Limonciello authored
A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443Signed-off-by:
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Mario Limonciello authored
The `DMUB_FW_VERSION` macro has a mistake in that the revision field is off by one byte. The last byte is typically used for other purposes and not a revision. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by:
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Evan Quan authored
The feature mask bit was not correctly cleared. Without that, the L2H and H2L interrupts cannot be enabled. Signed-off-by:
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Hong-lu Cheng authored
[why] Endless assert caused by LinesInDETChroma=0. [how] Don't floor for LinesInDETChroma=0 Tested-by:
Hong-lu Cheng <hong-lu.cheng@amd.com> Signed-off-by:
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Ilya Bakoulin authored
[Why] This display doesn't properly indicate link loss through DPCD bits such as CR_DONE / CHANNEL_EQ_DONE / SYMBOL_LOCKED / INTERLANE_ALIGN_DONE, which all remain set. In addition, DPCD200Eh doesn't match the value of DPCD204h in all cases. For these reasons, we can miss re-training the link, since we don't properly detect link loss with this display. [Why] Add display-specific workaround to read DPCD204h, so that we can detect link loss based on 128b132b-specific status bits in this register. Tested-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by:
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Zhigang Luo authored
port SRIOV VF missed changes from gfx_v9_0 to gfx_v9_4_3. Reviewed-by:
Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by:
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Mario Limonciello authored
If the securedisplay TA failed to load the first time, it's unlikely to work again after a suspend/resume cycle or reset cycle and it appears to be causing problems in futher attempts. Fixes: e42dfa66 ("drm/amdgpu: Add secure display TA load for Renoir") Reported-by:
Filip Hejsek <filip.hejsek@gmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2633Signed-off-by:
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