- 11 Mar, 2016 1 commit
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Sinan Kaya authored
Creating a QCOM directory for all QCOM DMA source files. Signed-off-by:
Sinan Kaya <okaya@codeaurora.org> Reviewed-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 21 Nov, 2015 1 commit
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Arnd Bergmann authored
As we are now passing the filter data as pointers to the drivers, we can take the final step and also pass the filter function the same way. I'm keeping this change separate, as there it's less obvious that this is a net win. Upsides of this are: - The ASoC drivers are completely independent from the DMA engine implementation, which simplifies the Kconfig logic and in theory allows the same sound drivers to be built in a kernel that supports different kinds of dmaengine drivers. - Consistency with other subsystems and drivers On the other hand, we have a few downsides: - The s3c24xx-dma driver now needs to be built-in for the ac97 platform device to be instantiated on s3c2440. - samsung_dmaengine_pcm_config cannot be marked 'const' any more because the filter function pointer needs to be set at runtime. This is safe as long we don't have multiple different DMA engines in thet same system at runtime, but is nonetheless ugly. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- 16 Nov, 2015 1 commit
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M'boumba Cedric Madianga authored
This patch adds support for the STM32 DMA controller. Signed-off-by:
M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 27 Oct, 2015 1 commit
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Peter Ujfalusi authored
Since the crossbar is needed for eDMA when it is used on OMAP like platforms (am335x/am437x and later DRA7xx), select the crossbar to be built if ARCH_OMAP is set. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 14 Oct, 2015 1 commit
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Peter Ujfalusi authored
Move the code out from arch/arm/common and merge it inside of the dmaengine driver. This change is done with as minimal (if eny) functional change to the code as possible to avoid introducing regression. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 24 Sep, 2015 1 commit
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Vinod Koul authored
the symbol CONFIG_IDMA64 should rather be CONFIG_INTEL_IDMA64 to conform to rest of the intel dmaengine drivers. This was found after sorting the entries and trying to place this odd one Suggested-by:
Linus Torvalds <torvalds@linux-foundation.org> Acked-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 24 Aug, 2015 1 commit
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Vinod Koul authored
dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 23 Aug, 2015 1 commit
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Lars-Peter Clausen authored
Add support for the Analog Devices AXI-DMAC DMA controller. This controller is a soft peripheral that can be instantiated in a FPGA and is often used in Analog Devices' reference designs for FPGA platforms. The peripheral has various configuration options that can be selected at synthesis time and influence the supported features of the instantiated peripheral, those options are represented as device-tree properties to allow the driver to behave accordingly. The peripheral has a zero latency architecture, which means it is possible to switch from one to the next descriptor without any delay. This is archived by having a internal queue which can hold multiple descriptors. The driver supports this, which means it will submit new descriptors directly to the hardware until the queue is full and not wait for a descriptor to complete before the next one is submitted. Interrupts are used for the descriptor queue flow control. Currently the driver supports SG, cyclic and interleaved slave DMA. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 21 Aug, 2015 1 commit
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Dave Jiang authored
The 32bit build is creating this warning. Since we don't expect anyone actually use this on 32bit, restrict ioatdma to be built only on x86_64. This issue has long existed and only reason it's surfacing due to code refactoring. drivers/dma/ioat/dma.c: In function 'ioat_timer_event': >> drivers/dma/ioat/dma.c:870:39: warning: passing argument 2 of 'ioat_cleanup_preamble' from incompatible pointer type if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) ^ drivers/dma/ioat/dma.c:577:13: note: expected 'u64 *' but argument is of type 'dma_addr_t *' static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, ^ Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 20 Aug, 2015 1 commit
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Emilio López authored
This patch adds support for the DMA engine present on Allwinner A10, A13, A10S and A20 SoCs. This engine has two kinds of channels: normal and dedicated. The main difference is in the mode of operation; while a single normal channel may be operating at any given time, dedicated channels may operate simultaneously provided there is no overlap of source or destination. Hardware documentation can be found on A10 User Manual (section 12), A13 User Manual (section 14) and A20 User Manual (section 1.12) Signed-off-by:
Emilio López <emilio@elopez.com.ar> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 18 Aug, 2015 1 commit
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Joachim Eastwood authored
Add support for DMA on NXP LPC18xx/43xx platforms which has a multiplexer in front of the PL080 dma request lines. The mux is a single register in the LPC18xx/43xx CREG block and can multiplex up to 4 request lines to each of the 16 lines on the PL080. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 28 Jul, 2015 1 commit
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Andy Shevchenko authored
Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of LPSS devices such as HSUART or SPI. The iDMA IP is attached for private usage on each host controller independently. While it has similarities with Synopsys DesignWare DMA, the following distinctions doesn't allow to use the existing driver: - 64-bit mode with corresponding changes in Hardware Linked List data structure - many slight differences in the channel registers Moreover this driver is based on the DMA virtual channels framework that helps to make the driver cleaner and easy to understand. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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- 16 Jul, 2015 1 commit
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Jun Nie authored
Add ZTE ZX296702 dma controller support. Only device tree probe is support currently. Signed-off-by:
Jun Nie <jun.nie@linaro.org> Reviewed-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 26 May, 2015 1 commit
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Robert Jarzmik authored
This is a new driver for pxa SoCs, which is also compatible with the former mmp_pdma. The rationale behind a new driver (as opposed to incremental patching) was : - the new driver relies on virt-dma, which obsoletes all the internal structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the functions - mmp_pdma allocates dma coherent descriptors containing not only hardware descriptors but linked list information The new driver only puts the dma hardware descriptors (ie. 4 u32) into the dma pool allocated memory. This changes completely the way descriptors are handled - the architecture behind the interrupt/tasklet management was rewritten to be more conforming to virt-dma - the buffers alignment is handled differently The former driver assumed that the DMA channel stopped between each descriptor. The new one chains descriptors to let the channel running. This is a necessary guarantee for real-time high bandwid...
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- 14 May, 2015 1 commit
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Peter Ujfalusi authored
The DRA7x has more peripherals with DMA requests than the sDMA can handle: 205 vs 127. All DMA requests are routed through the DMA crossbar, which can be configured to route selected incoming DMA requests to specific sDMA request. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 27 Apr, 2015 1 commit
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Jean Delvare authored
The xgene-dma driver is only useful on X-Gene SoC. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Rameshwar Prasad Sahu <rsahu@apm.com> Cc: Loc Ho <lho@apm.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 02 Apr, 2015 2 commits
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Xuelin Shi authored
The RaidEngine is a new FSL hardware used for Raid5/6 acceration. This patch enables the RaidEngine functionality and provides hardware offloading capability for memcpy, xor and pq computation. It works with async_tx. Signed-off-by:
Harninder Rai <harninder.rai@freescale.com> Signed-off-by:
Xuelin Shi <xuelin.shi@freescale.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Rameshwar Prasad Sahu authored
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy, scatter-gather memory copy, raid5 xor, and raid6 p+q offloading. Signed-off-by:
Rameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by:
Loc Ho <lho@apm.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 01 Apr, 2015 1 commit
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Alex Smith authored
This patch adds a driver for the DMA controller found in the Ingenic JZ4780. It currently does not implement any support for the programmable firmware feature of the controller - this is not necessary for most uses. It also does not take priority into account when allocating channels, it just allocates the first available channel. This can be implemented later. Signed-off-by:
Alex Smith <alex.smith@imgtec.com> Signed-off-by:
Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> [Updated for dmaengine api changes, Add residue support, couple of minor fixes] Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 17 Mar, 2015 1 commit
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Andy Shevchenko authored
Since the last and the only user of this driver is converted to use dw_dmac we can remove driver from the tree. Moreover, besides the driver is unmaintained a long time, it serves for the DesignWare DMA IP, for which we have already driver in the tree. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- 07 Mar, 2015 1 commit
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Andy Shevchenko authored
The HSU DMA is developed to support High Speed UART controllers found in particular on Intel MID platforms such as Intel Medfield. The existing implementation is tighten to the drivers/tty/serial/mfd.c driver and has a lot of disadvantages. Besides that we would like to get rid of the old HS UART driver in regarding to extending the 8250 which supports generic DMAEngine API. That's why the current driver has been developed. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 05 Feb, 2015 1 commit
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Andrew Bresticker authored
Add support for the IMG Multi-threaded DMA Controller (MDC) found on certain IMG SoCs. Currently this driver supports the variant present on the MIPS-based Pistachio SoC. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 24 Jan, 2015 1 commit
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Arnd Bergmann authored
Everything uses dmaengine now, so there is no reason to keep this around any longer. Thanks to everyone who was involved in moving the users over to use the dmaengine APIs. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Kukjin Kim <kgene@kernel.org>
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- 17 Nov, 2014 2 commits
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Ludovic Desroches authored
_relaxed version of readl and writel are not implemented on all architecture so COMPILE_TEST has to be removed in order to not cause some build failures. Signed-off-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Chen-Yu Tsai authored
The A23 SoC has the same dma engine as the A31 (sun6i), with a reduced amount of endpoints and physical channels. Add the proper config data and compatible string to support it. A slight difference in sun8i is an undocumented register needs to be toggled for dma to function. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 06 Nov, 2014 1 commit
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Ludovic Desroches authored
New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 28 Sep, 2014 1 commit
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Dan Williams authored
Per commit "77873803 net_dma: mark broken" net_dma is no longer used and there is no plan to fix it. This is the mechanical removal of bits in CONFIG_NET_DMA ifdef guards. Reverting the remainder of the net_dma induced changes is deferred to subsequent patches. Marked for stable due to Roman's report of a memory leak in dma_pin_iovec_pages(): https://lkml.org/lkml/2014/9/3/177 Cc: Dave Jiang <dave.jiang@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: David Whipple <whipple@securedatainnovations.ch> Cc: Alexander Duyck <alexander.h.duyck@intel.com> Cc: <stable@vger.kernel.org> Reported-by:
Roman Gushchin <klamm@yandex-team.ru> Acked-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
Dan Williams <dan.j.williams@intel.com>
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- 23 Sep, 2014 1 commit
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Fabio Estevam authored
MX6 processors also use the IMX_SDMA driver, so include it in the help text. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 08 Aug, 2014 1 commit
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Maxime Ripard authored
Fixes a compilation error when RESET_CONTROLLER is not enabled in the configuration. drivers/dma/sun6i-dma.c: In function 'sun6i_dma_probe': drivers/dma/sun6i-dma.c:911:2: error: implicit declaration of function 'devm_reset_control_get' [-Werror=implicit-function-declaration] Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reported-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 07 Aug, 2014 1 commit
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Guennadi Liakhovetski authored
Although this driver doesn't have any explicit compile-time architecture dependencies, it is better not to bloat kernels on those platforms, where this driver isn't needed, unless a compile test is being performed. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 04 Aug, 2014 1 commit
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Guennadi Liakhovetski authored
This patch adds a driver for NBPF DMAC IP cores from Renesas, designed for the AMBA AXI bus. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 30 Jul, 2014 1 commit
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Alexander Popov authored
Select DMA_ENGINE when DMA_OF is selected since of_dma_xlate_by_chan_id() from drivers/dma/of-dma.c uses dma_get_slave_channel() from drivers/dma/dmaengine.c This resolves error reported: drivers/built-in.o: In function `of_dma_xlate_by_chan_id': drivers/dma/of-dma.c:253: undefined reference to `dma_get_slave_channel' Signed-off-by:
Alexander Popov <a13xp0p0v88@gmail.com> Reported-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 25 Jul, 2014 1 commit
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Maxime Ripard authored
The Allwinner A31 has a 16 channels DMA controller that it shares with the newer A23. Although sharing some similarities with the DMA controller of the older Allwinner SoCs, it's significantly different, I don't expect it to be possible to share the driver for these two. The A31 Controller is able to memory-to-memory or memory-to-device transfers on the 16 channels in parallel. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 16 Jul, 2014 1 commit
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Sudeep Dutt authored
Select DMA_ENGINE instead of DMAENGINE and delete the default line as the default is 'n' anyways. Link: https://lkml.org/lkml/2014/7/14/90 Reported-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
Sudeep Dutt <sudeep.dutt@intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 12 Jul, 2014 1 commit
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Siva Yerramreddy authored
This patch implements DMA Engine API for DMA controller on MIC X100 Coprocessors. DMA h/w is shared between host and card s/w. Channels 0 to 3 are used by host and 4 to 7 are used by card. Since the DMA device doesn't show up as PCIe device, a virtual bus called mic bus is created and virtual devices are added on that bus to follow device model. Allowed dma transfer directions are host to card, card to host and card to card. Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Nikhil Rao <nikhil.rao@intel.com> Reviewed-by:
Sudeep Dutt <sudeep.dutt@intel.com> Signed-off-by:
Siva Yerramreddy <yshivakrishna@gmail.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 01 Jun, 2014 1 commit
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Fabio Estevam authored
The APBX-DMA block is also found on MX6Q/MX6DL chips. Update the help text accordingly. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 22 May, 2014 1 commit
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Jean Delvare authored
The pch_dma driver is for a companion chip to the Intel Atom E600 series processors. These are 32-bit x86 processors so the driver is only needed on X86_32. Add COMPILE_TEST as an alternative, so that the driver can still be build-tested elsewhere. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 30 Apr, 2014 1 commit
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Srikanth Thokala authored
This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by:
Srikanth Thokala <sthokal@xilinx.com> Acked-by:
Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by:
Levente Kurusa <levex@linux.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 16 Apr, 2014 1 commit
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Jean Delvare authored
VIDEO_TIMBERDALE selects TIMB_DMA which itself depends on MFD_TIMBERDALE, so VIDEO_TIMBERDALE should either select or depend on MFD_TIMBERDALE as well. I chose to make it depend on it because I think it makes more sense and it is consistent with what other options are doing. Adding a "|| HAS_IOMEM" to the TIMB_DMA dependencies silenced the kconfig warning about unmet direct dependencies but it was wrong: without MFD_TIMBERDALE, TIMB_DMA is useless as the driver has no device to bind to. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Mauro Carvalho Chehab <m.chehab@samsung.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 05 Apr, 2014 1 commit
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Andy Gross authored
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller found in the MSM 8x74 platforms. Each BAM DMA device is associated with a specific on-chip peripheral. Each channel provides a uni-directional data transfer engine that is capable of transferring data between the peripheral and system memory (System mode), or between two peripherals (BAM2BAM). The initial release of this driver only supports slave transfers between peripherals and system memory. Signed-off-by:
Andy Gross <agross@codeaurora.org> Tested-by:
Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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