- 15 Sep, 2020 12 commits
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Ville Syrjälä authored
Make a clean split between hpd pins for DDI vs. TC. This matches how the actual hardware is split. And with this we move the DDI/PHY->HPD pin mapping into the encoder init instead of having to remap yet again in the interrupt code. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-11-ville.syrjala@linux.intel.comReviewed-by:
José Roberto de Souza <jose.souza@intel.com>
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Ville Syrjälä authored
Currently DP/HDMI/DDI encoders init their hpd_pin from the connector init. Let's move it to the encoder init so that we don't need to add platform specific junk to the connector init (which is shared by all g4x+ platforms). Signed-off-by:
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Ville Syrjälä authored
No reason to stuff both DDI and TC port handling into the same function. Split it into two. Signed-off-by:
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Ville Syrjälä authored
gen11_hpd_detection_setup() is missing ports TC5/6. Add them. TODO: Might be nice to only enable the hpd detection logic for ports we actually have. Should be rolled out for all platforms if/when done... Signed-off-by:
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Ville Syrjälä authored
We have nice parametrized GEN11_{TC,TBT}_HOTPLUG() so nuke the overlapping defines. Signed-off-by: -
Ville Syrjälä authored
As with everything else VBT can now specify AUX CH H or I. Signed-off-by:
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Ville Syrjälä authored
VBT has ports H and I since version 217. Signed-off-by:
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Ville Syrjälä authored
AUX CH H/I need their power domains too. Signed-off-by:
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Ville Syrjälä authored
We need to go up to PORT_I (aka. TC6) these days. Signed-off-by:
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Ville Syrjälä authored
We need to go up to AUX_CH_I (aka. AUX CH USBC6) these days. Signed-off-by:
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Ville Syrjälä authored
Since the display hardware is all there even when INTEL_DISPLAY_ENABLED return false we have to be capable of shutting it down cleanly so as to not anger the hw. To that end let's reduce the effect of !INTEL_DISPLAY_ENABLE to just treating all outputs as disconnected. Should prevent anyone from automagically enabling any of them, while still allowing us to cleanly shut them down. v2: Put the check into the right place for CRT Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Having a mode where the display hardware is present but we try to pretend it isn't just leads to massive headaches when trying to reason what the fallout might be from skipping some random bits of programming. Let's just neuter INTEL_DISPLAY_ENABLED so that we treat the hardware as fully present, except we just don't register any outputs. That's still rather sketchy if the outputs are already enabled when the driver is loaded. I think the simplest solution would be to probe everything as normal and just return disconnected" from all .detect() hooks. That would avoid anything automagically enabling those outputs, but the driver could then shut things down using the normal codepaths. Signed-off-by:
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- 14 Sep, 2020 9 commits
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Rodrigo Vivi authored
Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com>
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Rodrigo Vivi authored
Signed-off-by: -
https://github.com/intel/gvt-linuxRodrigo Vivi authored
gvt-next-2020-09-10 - Cleanup command access flag (Yan) - New workaround cmd access fix (Colin) - MIA reset state fix (Colin) Signed-off-by:
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Ville Syrjälä authored
g4x+ sprites have an extra cdclk limitation listed for RGB formats. For some random reason I chose to use cpp>=4 as the check for that. While that does actually work let's deobfuscate it by checking for !is_yuv instead. I suspect is_yuv didn't exist way back when I originally write the code. Also drop the duplicate comment. Signed-off-by:
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Ville Syrjälä authored
Even if we're not doing downscaling we should account for some of the extra dotclock limitations for g4x+ sprites. In particular we must never exceed the 90% rule, and with RGB that limits actually drops to 80%. So instead of bailing out when upscaling let's clamp the scaling factor appropriately and go through the rest of calculation normally. By luck we already did the full calculations for the 1:1 case. Signed-off-by:
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Ville Syrjälä authored
The CACHE_MODE_0 save/restore was added without explanation in commit 1f84e550 ("drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)"). If there are any bits we care about those should be set explicitly during some appropriate init function. Let's assume it's all good and just nuke this magic save/restore. Signed-off-by:
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Ville Syrjälä authored
Originally added in commit 1f84e550 ("drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)") to fix some underruns. I suspect that was due to the trickle feed settings getting clobbered during suspend. We've been disabling trickle feed explicitly since commit 20f94967 ("drm/i915: Disable trickle feed via MI_ARB_STATE for the gen4") so this magic save/restore should no longer be needed. Signed-off-by:
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Ville Syrjälä authored
The FBC_CONTROL save restore is there just to preserve the compression interval setting. Since commit a68ce21b ("drm/i915/fbc: Store the fbc1 compression interval in the params") we've been explicitly setting the interval to a specific value, so the sace/restore is now entirely pointless. Signed-off-by:
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Ville Syrjälä authored
We don't save/restore PCH_PORT_HOTPLUG so no point in reseving space for the value. Signed-off-by:
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- 12 Sep, 2020 1 commit
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Rodrigo Vivi authored
Sync drm-intel-gt-next here so we can have an unified fixes flow. Signed-off-by:
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- 11 Sep, 2020 4 commits
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Ville Syrjälä authored
There's no real reason to stash away the DPIO PHY IOSF sideband port numbers for VLV/CHV. Just compute them at runtime in the sideband code. Gets rid of the oddball intel_init_dpio() function from the high level init flow. Signed-off-by:
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Jani Nikula authored
Logically part of the display restore. Note: This has been in place since the introduction of gmbus support. The gmbus code also does the resets before transfers. Is this really needed, or a historical accident? Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Logically part of the display save/restore. No functional changes. Reviewed-by:
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Jani Nikula authored
Disable all display feature flags when there are no pipes i.e. there is no display. This should help with not having to additionally check for HAS_DISPLAY() when a feature flag check would suffice. Also disable modeset and atomic driver features. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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- 10 Sep, 2020 7 commits
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Maarten Lankhorst authored
This function should be an int, not a bool. Presumably because we had the same 2 reverts in a slightly different way, git got confused. Thanks to Dan for reporting. :) The conflict is between the 3 reverts in drm-fixes: 4993a8a3 ("Revert "drm/i915: Remove i915_gem_object_get_dirty_page()"") ad5d95e4 ("Revert "drm/i915/gem: Async GPU relocations only"") 20561da3 ("Revert "drm/i915/gem: Delete unused code"") And the slightly different combined revert in drm-intel-gt-next, but with the same goal: 102a0a90 ("Revert "drm/i915/gem: Async GPU relocations only"") In the merge commit 1f4b2aca ("Merge tag 'drm-intel-gt-next-2020-09-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next") things went wrong, but the merge commit view now doesn't show any conflict anymore (as git tends to do when the resolution picks one or the other branch). The need to handle other than just true/false error codes in __reloc_entry_gpu was added in the dma_resv locking changes in c43ce123 ("drm/i915: Use per object locking in execbuf, v12.") Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Dave Airlie <airlied@redhat.com> [danvet: Explain this entire saga a lot better, adding tons of commit references. Also note that this was merged before full intel-gfx-CI results, only after BAT, since the breakage at the BAT run is already severe enough to block all pre-merge testing.] Fixes: 1f4b2aca ("Merge tag 'drm-intel-gt-next-2020-09-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next") Acked-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20200910111225.2184193-1-maarten.lankhorst@linux.intel.com
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Colin Xu authored
Although GVT doesn't support guest GuC, MIA core is still expected to be GS_MIA_IN_RESET after uc HW reset. Reviewed-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
Colin Xu <colin.xu@intel.com> Signed-off-by:
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Colin Xu authored
Without F_CMD_ACCESS, guest LRI cmd will fail due to "access to non-render register" when init below WAs: WaDisableDynamicCreditSharing: GAMT_CHKN_BIT_REG WaCompressedResourceSamplerPbeMediaNewHashMode: MMCD_MISC_CTRL So add F_CMD_ACCESS to the two MMIO. Reviewed-by:
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Yan Zhao authored
some registers cannot be cmd accessible. remove them from the list Reviewed-by:
Wang Zhi <zhi.a.wang@intel.com> Signed-off-by:
Yan Zhao <yan.y.zhao@intel.com> Signed-off-by:
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Yan Zhao authored
flag F_CMD_ACCESS represents whether an MMIO is able to be accessed by GPU commands. In this patch, 1. add interface to set this flag 2. rename intel_gvt_mmio_is_cmd_access() to intel_gvt_mmio_is_cmd_accessible() and update its description message. Reviewed-by:
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Yan Zhao authored
Flag F_CMD_ACCESSED is not used. just remove it. Reviewed-by:
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Yan Zhao authored
F_IN_CTX is an inaccurate flag name, because people may wrongly think all MMIOs in context image are with this flag. But actually, this flag is only for MMIOs both in GVT's save-restore list and in hardare logical context's image. Reviewed-by:
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- 09 Sep, 2020 1 commit
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Dave Airlie authored
Merge tag 'topic/nouveau-i915-dp-helpers-and-cleanup-2020-08-31-1' of git://anongit.freedesktop.org/drm/drm-misc into drm-next UAPI Changes: None Cross-subsystem Changes: * Moves a bunch of miscellaneous DP code from the i915 driver into a set of shared DRM DP helpers Core Changes: * New DRM DP helpers (see above) Driver Changes: * Implements usage of the aforementioned DP helpers in the nouveau driver, along with some other various HPD related cleanup for nouveau Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/11e59ebdea7ee4f46803a21fe9b21443d2b9c401.camel@redhat.com
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- 08 Sep, 2020 6 commits
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2020-09-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (Same content as drm-intel-gt-next-2020-09-04-3, S-o-b's added) UAPI Changes: (- Potential implicit changes from WW locking refactoring) Cross-subsystem Changes: (- WW locking changes should align the i915 locking more with others) Driver Changes: - MAJOR: Apply WW locking across the driver (Maarten) - Reverts for 5 commits to make applying WW locking faster (Maarten) - Disable preparser around invalidations on Tigerlake for non-RCS engines (Chris) - Add missing dma_fence_put() for error case of syncobj timeline (Chris) - Parse command buffer earlier in eb_relocate(slow) to facilitate backoff (Maarten) - Pin engine before pinning all objects (Maarten) - Rework intel_context pinning to do everything outside of pin_mutex (Maarten) - Avoid tracking GEM context until registered (Cc: stable, Chris) - Provide a fastpath for waiting on vma bindings (Chris) - Fixes to preempt-to-busy mechanism (Chris) - Distinguish the virtual breadcrumbs from the irq breadcrumbs (Chris) - Switch to object allocations for page directories (Chris) - Hold context/request reference while breadcrumbs are active (Chris) - Make sure execbuffer always passes ww state to i915_vma_pin (Maarten) - Code refactoring to facilitate use of WW locking (Maarten) - Locking refactoring to use more granular locking (Maarten, Chris) - Support for multiple pinned timelines per engine (Chris) - Move complication of I915_GEM_THROTTLE to the ioctl from general code (Chris) - Make active tracking/vma page-directory stash work preallocated (Chris) - Avoid flushing submission tasklet too often (Chris) - Reduce context termination list iteration guard to RCU (Chris) - Reductions to locking contention (Chris) - Fixes for issues found by CI (Chris) Signed-off-by:
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Dave Airlie authored
Commit '6f6a73c8' from Linus' tree The fixes reverts cause a bit of a conflict pain with intel next, start fixing it up here. Signed-off-by:
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git://anongit.freedesktop.org/drm/drmLinus Torvalds authored
Pull drm fixes from Dave Airlie: "The i915 reverts are going to be a bit of a conflict mess for next, so I decided to dequeue them now, along with some msm fixes for a ring corruption issue, that Rob sent over the weekend. Summary: i915: - revert gpu relocation changes due to regression msm: - fixes for RPTR corruption issue" * tag 'drm-fixes-2020-09-08' of git://anongit.freedesktop.org/drm/drm: Revert "drm/i915/gem: Delete unused code" Revert "drm/i915/gem: Async GPU relocations only" Revert "drm/i915: Remove i915_gem_object_get_dirty_page()" drm/msm: Disable the RPTR shadow drm/msm: Disable preemption on all 5xx targets drm/msm: Enable expanded apriv support for a650 drm/msm: Split the a5xx preemption record
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Linus Torvalds authored
Merge tag 'livepatching-for-5.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/livepatching/livepatching Pull livepatching fix from Petr Mladek: "Workaround for 'unreachable instruction' objtool warnings that happen with some compiler versions" * tag 'livepatching-for-5.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/livepatching/livepatching: Revert "kbuild: use -flive-patching when CONFIG_LIVEPATCH is enabled"
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
amd-drm-next-5.10-2020-09-03: amdgpu: - RAS fixes - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support in DC - Enable plane rotation - Rework pre-OS vram reservation handling during driver init - Add standard interface to dump GPU metrics table from SMU - Rework tiling and tmz state handling in atomic commits - Pstate fixes - Add voltage and power hwmon interfaces for renoir - SW CTF fixes - S/G display fix for Raven - Print client strings for vmfaults for vega and newer - Manual fan control fixes - Display updates - Reorg power management directory structure - Misc bug fixes - Misc code cleanups amdkfd: - Topology fixes - Add SMI events for thermal throttling and GPU resets radeon: - switch from pci_* to dma_* for dma allocations - PLL fix Scheduler: - Clean up priority levels UAPI: - amdgpu INFO IOCTL query update for TMZ state https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049 - amdkfd SMI event interface updates https://github.com/RadeonOpenCompute/rocm_smi_lib/tree/therm_thrott From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200903222921.4152-1-alexander.deucher@amd.com
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Dave Airlie authored
These commits caused a regression on Lenovo t520 sandybridge machine belonging to reporter. We are reverting them for 5.10 for other reasons, so just do it for 5.9 as well. This reverts commit 7ac2d253. Reported-by:
Harald Arnesen <harald@skogtun.org> Signed-off-by:
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