- 19 Oct, 2021 35 commits
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Guchun Chen authored
Otherwise, hw_id_name string is NULL for SDMA 2 and 3 when dumping ip version from VBIOS. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tao Zhou authored
Output a warning message if RAS TA returns UNSUPPORTED_ERROR_INJ status. v2: implement it in psp_ras_ta_check_status function. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
Create new function to check status returned by RAS TA. Signed-off-by:
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Agustin Gutierrez authored
This reverts commit 1445d967. This patch introduced a couple of dmesg warnings, this is not a valid approach anymore. For this reason, we are reverting this patch, and we need to revert the workaround patch. v2: squash in unused variable removal (Alex) Cc: Hanghong Ma <hanghong.ma@amd.com> Cc: Mark Broadworth <mark.broadworth@amd.com> Signed-off-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by:
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Agustin Gutierrez authored
This reverts commit 4874ecf5. Signed-off-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Nevenko Stupar authored
[Why] V3_4 is latest in use. [How] Add bios parser support for firmware_info_v3_4 along with some relevant fields it is also retrieving from dce_info and smu_info. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Tested-by:
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Aric Cyr authored
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Fix some issues such as DP2 problem, prefetch bandwidth calculation for DCN3.1 and others. * Increased Z9 latency and removed z10 save after dsc disable. * Revert a couple of bad changes. * Added missing PSR state patch. Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
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Jake Wang authored
[Why & How] Disable hdmistream and hdmichar root clocks when not being used. Reviewed-by:
Jake Wang <haonan.wang2@amd.com> Tested-by:
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Jake Wang authored
[Why] bios_golden_init will override dccg_init during init_hw. [How] Move dccg_init to after bios_golden_init. Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Jake Wang authored
[Why & How] Z10 save is done during PSR and bootup. DSC disable does not need to save for Z10. Reviewed-by:
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Jake Wang authored
[Why & How] Disable dpstreamclk, symclk32_se, and symclk32_le when not in use. Reviewed-by:
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Nikola Cornij authored
[why] The original latencies were causing underflow in some modes [how] Replace with the up-to-date watermark values based on new measurments Reviewed-by:
Ahmad Othman <ahmad.othman@amd.com> Acked-by:
Nikola Cornij <nikola.cornij@amd.com> Tested-by:
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Eric Yang authored
[Why] Z9 latency is higher than when we originally tuned the watermark parameters, causing underflow. Increasing the value until the latency issues is resolved. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Immediate flip can be enabled dynamically and has higher BW requirements when validating which voltage mode to use. If we validate when it's not set then potentially DCFCLK will be too low and we will underflow. [How] DM always requires support so always require it as part of DML input parameters. This can't be enabled unconditionally on older ASIC because it blocks some expected modes so only target DCN3.1 for now. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Jake Wang authored
[Why & How] Disable root clock for dsc when not being used. Reviewed-by:
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Mikita Lipski authored
[why] PSR_STATE2b was introduced on DMCUB side, but not on the driver side, which caused convert_psr_state helper function to return PSR_STATE_INVALID. That caused visual lagging during state transition. [how] Add PSR_STATE2b to dc_psr_state and convert_psr_state Reviewed-by:
Wyatt Wood <Wyatt.Wood@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Prefetch BW calculated is lower than the DML reference because of a porting error that's excluding cursor and row bandwidth from the pixel data bandwidth. [How] Change the dml_max4 to dml_max3 and include cursor and row bandwidth in the same calculation as the rest of the pixel data during vactive. Reviewed-by:
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Hansen authored
Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused Reviewed-by:
Hansen <Hansen.Dsouza@amd.com> Tested-by:
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Nikola Cornij authored
[why] The requirement is that image width up to 4096 shall be supported Reviewed-by:
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Lai, Derek authored
[Why] Error message on Linux when booting. [How] Removed power down on boot from DCN31 HW init to match DCN10 HW init. Reviewed-by:
Derek Lai <derek.lai@amd.com> Tested-by:
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Aric Cyr authored
[Why] Calculation of scaling ratio can result in a crash due to zero'd src or dst plane rects. [How] Validate that src and dst rects are valid before using for scaling calculations. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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Wenjing Liu authored
Hardware team has recommended to generically hard code this register to 0xFF as part of the effort to eventually remove this control. However we set it to 0xF instead. This causes 4 of audio 8ch to be muted. Reviewed-by:
Ariel Bernstein <eric.bernstein@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by:
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Michael Strauss authored
[WHAT] One of the current VPG power on calls is unnecessary Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Wenjing Liu authored
[why] Some DP2.0 RX requires us to set MST_EN even for SST configuration. We added this debug option so we can configure this temporary workaround for the RX. Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
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Jimmy Kizito authored
[Why] When rapidly plugging and unplugging a DP sink, detection link training can be mistakenly skipped. This is due to the hotplug processing occurring before the encoder assignment logic has had a chance to process the removal of a stream. The encoder that would be used for detection link training is then erroneously reported as already in use and detection link training is skipped. [How] During hot plug processing, only determine a link encoder to be unavailable for a particular link if it has been assigned to a different link. Reviewed-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] When copying a stream, the encoder assigned to it is copied too. Encoder assignment should only happen when executing the encoder assignment function link_encs_assign(). [How] Clear the link encoder pointer for copied stream. Reviewed-by:
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Jake Wang authored
[Why & How] Disable root clock for dpp when not being used. Reviewed-by:
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Roman Li authored
[Why] On renoir usb-c port stops functioning on resume after f/w update. New dmub firmware caused regression due to conflict with dmcu. With new dmub f/w dmcu is superseded and should be disabled. [How] - Disable dmcu for all dcn21. Check dmesg for dmub f/w version. The old firmware (before regression): [drm] DMUB hardware initialized: version=0x00000001 All other versions require this patch for renoir. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1735Acked-by:
Harry Wentland <harry.wentland@amd.com> Tested-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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YuBiao Wang authored
[Why] drm_irq_uninstall is called in irq_fini_hw so that irq is disabled in sw stage. SMU (and maybe other IP blocks) fini_hw will call irq_put for cleanup and the whole cleanup process will be skipped because of drm->irq_enable = false. [How] Move ip_fini_early before irq_fini_hw. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Jonathan Kim authored
ROCr needs to be able to identify all devices that have direct access to fine grain memory, which should include CPUs that are connected to GPUs over xGMI. The GPU hive ID can be mapped onto the CPU hive ID since the CPU is part of the hive. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Tao Zhou authored
Some registers' access will fail without PSP RL after resume. Signed-off-by:
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Lang Yu authored
We should unreference a gem object instead of an amdgpu bo here. Fixes: fd9a9f88 ("drm/amdgpu: Use GEM obj reference for KFD BOs") Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
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- 14 Oct, 2021 4 commits
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Alex Deucher authored
Missed a few asics. v2: update comment Fixes: 82d05736 ("drm/amdgpu/amdgpu_psp: convert to IP version checking") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
VEGA20 is 11.0.2, but it's handled by powerplay, not swsmu. Fixes: a8967967 ("drm/amdgpu/amdgpu_smu: convert to IP version checking") Reviewed-by:
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Philip Yang authored
When creating unregistered new svm range to recover retry fault, avoid new svm range to overlap with ranges or userptr ranges managed by TTM, otherwise svm migration will trigger TTM or userptr eviction, to evict user queues unexpectedly. Change helper amdgpu_ttm_tt_affect_userptr to return userptr which is inside the range. Add helper svm_range_check_vm_userptr to scan all userptr of the vm, and return overlap userptr bo start, last. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Thelford Williams authored
Size can be any value and is user controlled resulting in overwriting the 40 byte array wr_buf with an arbitrary length of data from buf. Signed-off-by:
Thelford Williams <tdwilliamsiv@gmail.com> Signed-off-by:
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- 13 Oct, 2021 1 commit
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Alex Deucher authored
Was missed in the conversion to IP version checking. Fixes: af3b89d3 ("drm/amdgpu/smu11.0: convert to IP version checking") Reviewed-by:
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