- 27 Sep, 2023 7 commits
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Ville Syrjälä authored
Using the DSB for LUT loading during full modesets would require some actual though. Let's just use mmio for the time being. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-12-ville.syrjala@linux.intel.comReviewed-by:
Uma Shankar <uma.shankar@intel.com>
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Ville Syrjälä authored
Writing specific transcoder registers (and as it turns out, the legacy LUT as well) via DSB needs a magic sequence to emit non-posted register writes. Add a helper for this. Signed-off-by:
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Ville Syrjälä authored
Add a function for emitting masked register writes. Note that the mask is implemented through byte enables, so can only mask off aligned 8bit sets of bits. Signed-off-by:
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Ville Syrjälä authored
Add a helper for emitting a number of DSB NOOPs commands. Signed-off-by:
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Ville Syrjälä authored
Add some defines to specify what goes inside certain DSB instructions. Signed-off-by:
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Ville Syrjälä authored
Define all the DSB register bits so I don't have to look through bspec to find them. Signed-off-by:
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Ville Syrjälä authored
Avoid the locking overhead for DSB registers. We don't need the locks and intel_dsb_commit() in particular needs to be called from the vblank evade critical section and thus needs to be fast. Signed-off-by:
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- 26 Sep, 2023 2 commits
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Jani Nikula authored
Avoid including the world from headers when forward declarations suffice. Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921155325.3851197-1-jani.nikula@intel.com
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Jani Nikula authored
Convert aux_ch_name() to a helper that prints a string to a caller provided buffer, and use it to get more consistent aux channel debugs. Now that all users of aux_ch_name() are in intel_dp_aux.c, we can make it static too. Signed-off-by:
Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230922105645.3991066-1-jani.nikula@intel.com
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- 25 Sep, 2023 2 commits
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Gustavo Sousa authored
Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C behavior. If we do not properly reset them, we would miss delivery of interrupts if a pending bit is set when enabling IRQs. As an example, the display part of our probe routine contains paths where we wait for vblank interrupts. If a display interrupt was already pending when enabling IRQs, we would time out waiting for the vblank. Avoid the potential issue by clearing GFX_MSTR_IRQ as part of the IRQ reset. v2: - Move logic from gen11_gt_irq_reset() to dg1_irq_reset(). (Matt) BSpec: 50875, 54028 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230920195351.59421-2-gustavo.sousa@intel.com
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Tvrtko Ursulin authored
Recent refactoring left an unsightly block of empty lines. Remove them. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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- 22 Sep, 2023 1 commit
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Balasubramani Vivekanandan authored
Separate the printing of display version and feature flags from the main driver probe to inside the display initialization. This is in alignment with isolating the display code from the main driver and helps Xe driver to resuse it. v2: Replace drm_info_printer with drm_debug_printer (Jani) Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230921105954.2002469-1-balasubramani.vivekanandan@intel.com
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- 21 Sep, 2023 25 commits
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Ville Syrjälä authored
We have the same h/vsync_end vs. h/vtotal quirk in the VBT parser that was also present in EDID parser. Adjust the VBT parser the same way as was done for hte EDID parser to fixup h/vsync_end instead of h/vtotal. While I'm not currently aware of any machines that need this for the VBT it seems prudent to keep both parsers in sync. And while at it let's add some debugs here as well. A bit lackluster but didn't feel like plumbing the connector all the way down at this time. Signed-off-by:
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Stanislav Lisovskiy authored
Introduce correspondent definitions for choosing between CD2X CDCLK and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are defined with PLL CDCLK as source, so simply set it. Also skl_cdclk_decimal() shouldn't be set in CDCLK_CTL anymore, so skip it for display version 20 and above. v2: - Remove unneeded comment and use REG_BIT() (Matt Roper) - Rename CDCLK_SOURCE_SEL_CDCLK_PLL() to MDCLK_SOURCE_SEL_CDCLK_PLL to match spec (Lucas) Signed-off-by:Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-22-lucas.demarchi@intel.com
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Matt Roper authored
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The overall programming and requirements to enter DC states are similar to those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit as they did previously. Bspec: 68851, 68857, 68886, 69115 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-21-lucas.demarchi@intel.com
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Ravi Kumar Vodapalli authored
Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+, so reuse the code. PGPICA1 contains type-C capable port slices which requires the well to power powered up, so add new power well definition for it. The DC_OFF fake power well will be added in a follow up commit. v2: Do not rmw as bit 31 is the only R/W bit in the register (Matt Roper) BSpec: 68886 Signed-off-by:
Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
Add a new CDCLK table for Lunar Lake. v2: - Remove mdclk from the table as it's not needed (Matt Roper) - Update waveform values to the latest from spec (Matt Roper) - Rename functions and calculation to match by pixel rate (Lucas) v3: Keep only the table: as far as intel_pixel_rate_to_cdclk() is concerned, the minimum cdclk should still be half the pixel rate on Xe2 (bspec 68858: "Pipe maximum pixel rate = 2 * CDCLK frequency * Pipe Ratio") (Matt Roper) Bspec: 68861, 68858 Signed-off-by: -
Lucas De Marchi authored
LNL's south display uses the same table as MTP. Check for LNL's fake PCH to make it consistent with the other checks. The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in other cases, uses the same as the previous platform. Bspec: 68971, 20124 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
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Lucas De Marchi authored
Xe2_LPD also needs workaround 15010685871. While adding the new display version, also re-order the condition to follow the convention of new version first. v2: Remove redundant HAS_CDCLK_SQUASH(). As the platform or IP version needing the workaround are handpicked, there is no need to also check if tha platform has squashing support (Matt Roper) Signed-off-by: -
Gustavo Sousa authored
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the extra programming for hotplug inversion and DDI HPD filter duration is not necessary anymore. As mtp_hpd_irq_setup() is reasonably small, prefer to fork it into a new function for Xe2_LPD instead of adding a platform check. v2: Add extra bspec reference and fix missing else (Matt Roper) BSpec: 68970, 69940 Signed-off-by:
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Juha-Pekka Heikkilä authored
Enable odd size and panning for planar yuv formats. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by:
Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> Reviewed-by:
Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by:
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Luca Coelho authored
Starting from display version 20, we need to read the pin assignment from the IOM TCSS_DDI_STATUS register instead of reading it from the FIA. We use the pin assignment to decide the maximum lane count. So, to support this change, add a new lnl_tc_port_get_max_lane_count() function that reads from the TCSS_DDI_STATUS register and decides the maximum lane count based on that. BSpec: 69594 Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Gustavo Sousa authored
Differently from previous version, Xe2_LPD groups all port AUX interrupt bits into PICA interrupt registers. While at it, drop some trailing newlines. BSpec: 68958, 69697 Signed-off-by:
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Lucas De Marchi authored
The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD: now they are all in a single range, with CH_A and CH_B coming right after the USBC instances. Like was done when moving registers to PICA, use a helper macro to remap the ch passed to an index that can be used to calculate the right offset. Signed-off-by:
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Lucas De Marchi authored
XELPDP_DP_AUX_CH_CTL() and XELPDP_DP_AUX_CH_DATA() use 2 ranges. Prefer using _PICK_EVEN_2RANGES() over PICK(). Signed-off-by:
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Lucas De Marchi authored
Fix some whitespace issues for register definitions and keep the defines for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with the bit definition. While at it add a TODO entry that those defines shouldn't be using an implicit dev_priv. Signed-off-by:
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Clint Taylor authored
Do not read DE_RRMR register after display version 20. This register contains display state information during GFX state dumps. Bspec: 69456 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by:
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Matt Roper authored
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded to 0 since compression isn't ready; we need to make sure this doesn't cause the display code to go back to trying to write this register. Signed-off-by:
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Stanislav Lisovskiy authored
We now start calculating relative plane data rate for cursor plane as well, as instructed by BSpec and also treat cursor plane same way as other planes, when doing allocation, i.e not using fixed allocation for cursor anymore. Bspec: 68907 Signed-off-by:
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Gustavo Sousa authored
Xe2_LPD doesn't have south display engine on a PCH, it's actually on the SoC die (while north display engine is on compute die). As such it makes no sense to go through the PCI devices looking for an ISA bridge. The approach used by BXT/GLK can't be used here since leaving it with PCH_NONE would mean taking the wrong code paths. For the places we currently use a PCH check, it's enough for now to just check the north display version. Use that to define a fake PCH to be used across the driver. Eventually these PCH checks may need to be re-designed as this is already the third platform using/needing a fake PCH. v2: Match on display IP version rather than on platform (Matt Roper) v3: Extend and clarify commit message (Matt Roper / Ville) Signed-off-by:
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Lucas De Marchi authored
Follow the convention of checking the last platform first and reword the comment to convey there are more platforms than just DG1. Reviewed-by:
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Clint Taylor authored
If a particular pipe is disabled by fuse also remove the FBC for that pipe. Bspec: 69464 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by:
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Matt Roper authored
FBC is no longer limited by pipe: add the defines for pipes B and C that will be used by platforms supporting FBC on such pipes. Bspec: 68881, 68904 Signed-off-by:
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Balasubramani Vivekanandan authored
Add Lunar Lake platform definitions for i915 display. The support for LNL will be added to the xe driver, with i915 only driving the display side. Xe2 display is derived from the Xe_LPD+ IP; additional feature deltas will be introduced in subsequent patches, so here it's just adding a separate xe2_lpd_display struct. v2: Use a LPDP_FEATURES macro (Matt Roper) Signed-off-by:
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Lucas De Marchi authored
Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline for Xe2_LPD and will allow to see the delta more easily. v2: Move everything from xe_lpdp_display to the new macro and remove the version setting: it's not needed with GMD_ID. Signed-off-by: -
Ville Syrjälä authored
This reverts commit 959fb1a6. Looks like the core MST code might not call i2c_adapter() for us in time, and thus creating the ddc symlink will fail. This will in fact fail the entire connector registration, but the MST code doesn't really seem to care about that and blindly plows ahead. All we may get in the logs is a nearly back to back register+unregister debug messages: [drm:drm_dp_mst_connector_late_register [drm_display_helper]] registering DPMST remote bus for card0-DP-7 [drm:intel_dp_hpd_pulse [i915]] DPRX ESI: 42 00 00 02 [drm:drm_dp_mst_connector_early_unregister [drm_display_helper]] unregistering DPMST remote bus for card0-DP-7 Untangling the initialization order may take some real work, so let's just revert the ddc symlink addition for now... Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9357 Fixes: 959fb1a6 ("drm/i915/mst: Populate connector->ddc") Signed-off-by:
Karthik B S <karthik.b.s@intel.com>
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Jani Nikula authored
Add a note that fec_enable actually means FEC is to be enabled explicitly. 128b/132b always has FEC enabled, the driver doesn't need to enable it separately, and fec_enable will be false. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 20 Sep, 2023 3 commits
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Ville Syrjälä authored
Implement low refresh rate (LRR) where we change the vblank length by hand as requested, but otherwise keep the timing generator running in non-VRR mode (ie. fixed refresh rate). The panel itself must support VRR for this to work, and only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that we need to make the switch properly. The double buffer latching happens at the start of transcoders undelayed vblank. The other thing that we change is TRANS_VBLANK.VBLANK_END but the hardware entirely ignores that in DP mode. But I decided to keep writing it anyway just to avoid more special cases in readout/state check. v2: Document that TRANS_VBLANK.VBLANK_END is ignored by the hardware v3: Reconcile with VRR fastset Adjust update_lrr flag behaviour Make sure timings stay within VRR range v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi) Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi) TODO: Hook LRR into the automatic DRRS downclocking stuff? Cc: Manasi Navare <navaremanasi@chromium.org> Signed-off-by:Manasi Navare <navaremanasi@chromium.org>
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Ville Syrjälä authored
Whenever we change the actual transcoder timings (clock via seamless M/N, full modeset, (or soon) vtotal via LRR) we want the timing generator to be in non-VRR during the commit. Warn if we forgot to turn VRR off prior to vblank evasion. Cc: Manasi Navare <navaremanasi@chromium.org> Signed-off-by:
Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
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Ville Syrjälä authored
We should be able to change any of the VRR parameters during fastsets as long as we toggle VRR off at the start and then back on at the end. The transcoder will be running in non-VRR mode during the transition. Co-developed-by:
Sean Paul <seanpaul@chromium.org>
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