- 28 Jul, 2020 3 commits
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Sharat Masetty authored
This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by:
Sharat Masetty <smasetty@codeaurora.org> Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-6-git-send-email-akhilpo@codeaurora.orgSigned-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Sharat Masetty authored
This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by:
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Sai Prakash Ranjan authored
Add "qcom,replicator-loses-context" property to the replicator in Always-on domain in SC7180 SoC to enable coresight replicator driver to handle this variation of replicator designs. Reviewed-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/5072d94849cfaee46748d26ac997212fb2d783c2.1591708204.git.saiprakash.ranjan@codeaurora.orgSigned-off-by:
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- 27 Jul, 2020 3 commits
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Sai Prakash Ranjan authored
Define iommus property for Coresight ETR component in SC7180 SoC with the SID and mask to enable SMMU translation for this master. Signed-off-by:
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Sai Prakash Ranjan authored
Add "qcom,skip-power-up" property to skip powering up ETM on SC7180 SoC to workaround a hardware errata where CPU watchdog counter is stopped when ETM power up bit is set (i.e., when TRCPDCR.PU = 1). Reviewed-by:
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Ravi Kumar Bokka authored
This patch adds properties to the qfprom node to enable fuse blowing. Signed-off-by:
Ravi Kumar Bokka <rbokka@codeaurora.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200710073439.v5.4.I70c17309f8b433e900656d7c53a2e6b61888bb68@changeidSigned-off-by:
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- 22 Jul, 2020 2 commits
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Sandeep Maheswaram authored
Adding maximum speed property for DWC3 USB node which can be used for setting interconnect bandwidth. Signed-off-by:
Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1595317489-18432-3-git-send-email-sanm@codeaurora.orgSigned-off-by:
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Sai Prakash Ranjan authored
Add "arm,coresight-loses-context-with-cpu" property to coresight ETM nodes to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by:
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- 19 Jul, 2020 1 commit
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Nisha Kumari authored
This patch adds devicetree nodes for LAB and IBB regulators. Signed-off-by:
Nisha Kumari <nishakumari@codeaurora.org> [sumits: Updated for better compatible strings and names] Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> Link: https://lore.kernel.org/r/20200622124110.20971-4-sumit.semwal@linaro.orgSigned-off-by:
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- 17 Jul, 2020 2 commits
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Rajendra Nayak authored
Add the OPP tables for DSI and MDP based on the perf state/clk requirements, and add the power-domains property to specify the scalable power domain. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
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Rajendra Nayak authored
Add the OPP tables for DSI and MDP based on the perf state/clk requirements, and add the power-domains property to specify the scalable power domain. Tested-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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- 16 Jul, 2020 6 commits
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Sibi Sankar authored
All the platforms using SC7180 SoC are expected to have the wlan firmware memory statically mapped by the Trusted Firmware. Hence move back the qcom,msa-fixed-perm property to the SoC dtsi. Reviewed-by:
Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200716191746.23196-1-sibis@codeaurora.orgSigned-off-by:
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Stephan Gerhold authored
A3U/A5U both use a Bosch BMC150 accelerometer/magnetometer combo. The chip provides two separate I2C devices for the accelerometer and magnetometer that are already supported by the bmc150-accel and bmc150-magn driver. The only difference between A3U/A5U is the way the sensor is mounted on the mainboard - set the mount-matrix in the device-specific device tree part to handle that difference. Co-developed-by:
Michael Srba <michael.srba@seznam.cz> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200622151751.408995-5-stephan@gerhold.netSigned-off-by:
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Stephan Gerhold authored
Commit c240f29e ("arm64: dts: set the default i2c pin drive strength to 16mA") changed the default drive-strength for I2C pins in msm8916-pins.dtsi to the maximum possible (16 mA). While this makes sense for apq8016-sbc (DB410c) where you can connect an arbitrary amount of I2C devices with level shifters etc, there is no need to use a higher drive strength for other MSM8916 devices. The minimum drive strength (2 mA) seems to be totally sufficient to have everything work there. With the short pinctrl nodes introduced earlier we can easily override the drive-strength only for apq8016-sbc now. Use that and change the default back to 2 mA. i2c1_default/i2c5_default are already using 2 mA because they were added separately later and are not used in apq8016-sbc. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Stephan Gerhold authored
So far we have been separating pinctrl entries into pinmux/pinconf. It turns out it is also possible to combine them: The advantage is that the device tree is overall more concise because the "pins" to configure just need to be specified once, not separately for pinmux/pinconf. Using the simpler form only for new entries would be rather confusing. This commit makes all MSM8916 device trees use the simplfied form. Signed-off-by:
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Stephan Gerhold authored
It is helpful to be able to see all hardware components in one part of the device tree, without having to scroll over the large amount of regulator/pinctrl nodes. Keep those separated at the end of the file to make navigation a bit easier. This also makes it consistent with the order used in apq8016-sbc.dtsi. Signed-off-by:
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Bjorn Andersson authored
Now that we don't need the intermediate syscon to represent the TCSR mutexes, update the dts to describe the TCSR mutex directly under /soc. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200622075956.171058-5-bjorn.andersson@linaro.orgSigned-off-by:
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- 15 Jul, 2020 2 commits
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Rakesh Pillai authored
The wlan firmware memory is statically mapped in the Trusted Firmware, hence the wlan driver does not need to map/unmap this region dynamically. Hence add the property to indicate the wlan driver to not map/unamp the firmware memory region dynamically. Also add the chain1 voltage supply for wlan. Reviewed-by:
Rakesh Pillai <pillair@codeaurora.org> Link: https://lore.kernel.org/r/1594615586-17055-1-git-send-email-pillair@codeaurora.orgSigned-off-by:
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Douglas Anderson authored
The WiFi supplies that were added recently can't have done anything useful because they were missing the "-supply" suffix. Booting without the "-supply" suffix would give these messages: ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-0.8-cx-mx not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.8-xo not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.3-rfa not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-3.3-ch0 not found, using dummy regulator Let's add the "-supply" suffix. Tested-by:
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- 14 Jul, 2020 1 commit
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Eric Biggers authored
Add the vendor-specific registers and clock for Qualcomm ICE (Inline Crypto Engine) to the device tree node for the UFS host controller on sdm845, so that the ufs-qcom driver will be able to use inline crypto. Use a separate register range rather than extending the main UFS range because there's a gap between the two, and the ICE registers are vendor-specific. (Actually, the hardware claims that the ICE range also includes the array of standard crypto configuration registers; however, on this SoC the Linux kernel isn't permitted to access them directly.) Signed-off-by:
Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20200710072013.177481-4-ebiggers@kernel.orgSigned-off-by:
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- 13 Jul, 2020 6 commits
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Reviewed-by:
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sdm845. Reviewed-by:
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Rajendra Nayak authored
qup has a requirement to vote on the performance state of the CX domain in sc7180 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Reviewed-by:
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Rajendra Nayak authored
qup has a requirement to vote on the performance state of the CX domain in sdm845 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1593506712-24557-2-git-send-email-rnayak@codeaurora.orgSigned-off-by:
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sc7180 Reviewed-by:
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sdm845 Reviewed-by:
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- 09 Jul, 2020 1 commit
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Sibi Sankar authored
Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs. Tested-by:
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- 08 Jul, 2020 1 commit
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Sibi Sankar authored
Having a non-MSA (Modem Self-Authentication) SID bypassed breaks modem sandboxing i.e if a transaction were to originate from it, the hardware memory protections units (XPUs) would fail to flag them (any transaction originating from modem are historically termed as an MSA transaction). Drop the unused non-MSA modem SID on SC7180 SoCs and cheza so that SMMU continues to block them. Tested-by:
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- 02 Jul, 2020 2 commits
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Bjorn Andersson authored
Add a simple-mfd representing IMEM on SDM845 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Bjorn Andersson authored
Add a simple-mfd representing IMEM on QCS404 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Reviewed-by:
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- 30 Jun, 2020 1 commit
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Sibi Sankar authored
Add OPP tables required to scale DDR/L3 per freq-domain on SC7180 SoCs. Reviewed-by:
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- 25 Jun, 2020 1 commit
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Akash Asthana authored
Add interconnect ports for GENI QUPs and QSPI to set bus capabilities. Signed-off-by:
Akash Asthana <akashast@codeaurora.org> Link: https://lore.kernel.org/r/1592908737-7068-9-git-send-email-akashast@codeaurora.orgSigned-off-by:
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- 24 Jun, 2020 1 commit
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Sivaprakash Murugesan authored
IPQ8074 has two super speed usb ports, add phy and dwc3 nodes to enable them. Signed-off-by:
Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1591625479-4483-6-git-send-email-sivaprak@codeaurora.orgSigned-off-by:
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- 23 Jun, 2020 7 commits
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Konrad Dybcio authored
Add properties required for the bootloader to select the correct bootloader blob. They have been removed from the SoC device tree as they should be set on a per-device basis. Signed-off-by:
Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-11-konradybcio@gmail.comSigned-off-by:
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Konrad Dybcio authored
Add PSCI node to enable multi-processor startup. Note that not every 8994 device firmware supports PSCI, and even if, then it can only start the cores and not shut them down. Signed-off-by:
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Konrad Dybcio authored
Add the CPU PMU to get perf support for hardware events. Signed-off-by:
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Konrad Dybcio authored
Add support for I2C and SPI buses to enable peripherals such as touchscreens or sensors. Also add DMA nodes, configuration and BLSP2 UART2 interface. Signed-off-by:
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Konrad Dybcio authored
Enable support for SDHCI on msm8994-based devices. Signed-off-by:
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Konrad Dybcio authored
Add a proper CPU map to enable the use of all 8 cores. Signed-off-by:
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Konrad Dybcio authored
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by:
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