- 03 Jun, 2022 23 commits
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Aurabindo Pillai authored
DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Add support for the GPIO changes for DCN3.2.x. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2.x interrupt support. Signed-off-by:
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Aurabindo Pillai authored
DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by:
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Aurabindo Pillai authored
Add register headers for DCN 3.2.0 and 3.2.1. Signed-off-by:
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Aurabindo Pillai authored
Add DCN3.2 asic identifiers. Signed-off-by:
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Aurabindo Pillai authored
Add new structures for DCN 3.2.x. Signed-off-by:
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Stanley.Yang authored
SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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pengfuyuan authored
Fix spelling typo in comments. Reported-by:
k2ci <kernel-bot@kylinos.cn> Signed-off-by:
pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by:
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Evan Quan authored
The feature is ready with latest 78.39.0 PMFW. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
To fit the latest 78.39.0 PMFW. Signed-off-by:
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Evan Quan authored
There is some problem with average frequency reading. Thus, we switch to the target frequency reading instead. Signed-off-by:
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Mitchell Augustin authored
Removed trailing whitespace from end of line in amdgpu_device.c Signed-off-by:
Mitchell Augustin <kernel@mitchellaugustin.com> Signed-off-by:
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Alex Deucher authored
Use IP version rather than asic type. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
Drop extra cases in the default case. Reviewed-by:
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Leung, Martin authored
why: lut pipeline will be hooked up differently in some asics need to add new interfaces how: add them Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Martin <martin.leung@amd.com> Signed-off-by:
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Evan Quan authored
Suppress the compile warning below: drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1292 gfx_v11_0_rlc_backdoor_autoload_copy_ucode() warn: should '1 << id' be a 64 bit type? Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Evan Quan authored
Suppress the following compile warnings: >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v11_0_pptable.h:163:17: warning: field smc_pptable within 'struct smu_11_0_powerplay_table' is less aligned than 'PPTable_t' and is usually due to 'struct smu_11_0_powerplay_table' being packed, which can lead to unaligned accesses [-Wunaligned-access] PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h ^ 1 warning generated. -- >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v11_0_7_pptable.h:193:17: warning: field smc_pptable within 'struct smu_11_0_7_powerplay_table' is less aligned than 'PPTable_t' and is usually due to 'struct smu_11_0_7_powerplay_table' being packed, which can lead to unaligned accesses [-Wunaligned-access] PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h ^ 1 warning generated. -- >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0_pptable.h:161:12: warning: field smc_pptable within 'struct smu_13_0_powerplay_table' is less aligned than 'PPTable_t' and is usually due to 'struct smu_13_0_powerplay_table' being packed, which can lead to unaligned accesses [-Wunaligned-access] Signed-off-by: -
Philip Yang authored
Migration range from system memory to VRAM, if system page can not be locked or unmapped, we do partial migration and leave some pages in system memory. Several bugs found to copy pages and update GPU mapping for this situation: 1. copy to vram should use migrate->npage which is total pages of range as npages, not migrate->cpages which is number of pages can be migrated. 2. After partial copy, set VRAM res cursor as j + 1, j is number of system pages copied plus 1 page to skip copy. 3. copy to ram, should collect all continuous VRAM pages and copy together. 4. Call amdgpu_vm_update_range, should pass in offset as bytes, not as number of pages. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Lang Yu authored
The kfd_bo_list is used to restore process BOs after evictions. As page tables could be destroyed during evictions, we should also update pinned BOs' page tables during restoring to make sure they are valid. So for pinned BOs, 1, Validate them and update their page tables. 2, Don't add eviction fence for them. v2: - Don't handle pinned ones specially in BO validation.(Felix) Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Acked-by:
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Philip Yang authored
Flush TLBs when existing PDEs are updated because a PTB or PDB moved, but avoids unnecessary TLB flushes when new PDBs or PTBs are added to the page table, which commonly happens when memory is mapped for the first time. Suggested-by:
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Sunil Khatri authored
Add IP GC 10.3.7 in the list of target to have tmz enabled by default. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Mario Limonciello authored
Loading amdgpu on GC 10.3.7 shows an ERR level message: `kfd kfd: amdgpu: GC IP 0a0307 not supported in kfd` Add these targets to match yellow carp structures. Reported-by:
David Chang <david.chang@amd.com> Reviewed-by:
Jesse(Jie) Zhang <Jesse.Zhang@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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- 01 Jun, 2022 17 commits
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Philip Yang authored
MMU notifier callback may pass in mm with mm->mm_users==0 when process is exiting, use mmget_no_zero to avoid accessing invalid mm in deferred list work after mm is gone. Signed-off-by:
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Candice Li authored
Adjust the sequence for ras late init and separate ras reset error status from query status. v2: squash in fix from Candice Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Stanley.Yang authored
Fix aldebaran ras supported check on SRIOV guest side, the previous check conditicon block all ras feature on baremetal Signed-off-by:
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Aurabindo Pillai authored
This code should be executed. Signed-off-by:
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sunliming authored
This symbol is not used outside of gfx_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1945:6: warning: no previous prototype for function 'gfx_v11_0_rlc_stop' [-Wmissing-prototypes]. Reported-by:
sunliming <sunliming@kylinos.cn> Signed-off-by:
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sunliming authored
Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5873:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough]. Reported-by:
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Roman Li authored
[Why] Wrong fb offset results in dmub f/w errors and white screen. [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 [How] Read aper_base from mmhub because GC is off by default v2: use BAR for passthrough (Alex) Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Alex Deucher authored
Supports AV1. Mesa already has support for this and doesn't rely on the kernel caps for yellow carp, so this was already working from an application perspective. Fixes: 55439817 ("amdgpu/nv.c - Added video codec support for Yellow Carp") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2002Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Jiapeng Chong authored
This symbol is not used outside of imu_v11_0.c, so marks it static. Fixes the following w1 warning: drivers/gpu/drm/amd/amdgpu/imu_v11_0.c:302:6: warning: no previous prototype for ‘program_imu_rlc_ram’ [-Wmissing-prototypes]. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Aric Cyr authored
This version brings along the following fixes: * Changes to DP LT fallback behavior to more closely match the DP standard * Added new interfaces for lut pipeline * Restore ref_dtblck value when clk struct is cleared in init_clocks * Fixes DMUB outbox trace in S4 * Fixes lingering DIO FIFO errors when DIO no longer enabled * Reads Golden Settings Table from VBIOS Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Ilya authored
[Why] It's possible for some fallback scenarios to result in infinite looping during link training. [How] This change modifies DP LT fallback behavior to more closely match the DP standard. Keep track of the link rate during the EQ_FAIL fallback, and use it as the maximum link rate for the CR sequence. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Tested-by:
Ilya <Ilya.Bakoulin@amd.com> Signed-off-by:
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Alvin authored
[Description] ref_dtbclk value is assigned in clk_mgr_construct, but the clks struct is cleared in init_clocks. Make sure to restore the value or we will get 0 value for ref_dtbclk in DCN31. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Hung, Cruise authored
[Why] DMUB Outbox0 read/write pointer not sync after resumed from S4. And that caused old traces were sent to outbox. [How] Disable DMUB Outbox0 interrupt and clear DMUB Outbox0 read/write pointer when resumes from S4. And then enable Outbox0 interrupt before starts DMCUB. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Cruise Hung <Cruise.Hung@amd.com> Signed-off-by:
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hengzhou authored
[WHY] Very low rate to cause memory access issue while resetting DMCUB after the halt command was sent to it. The process of stopping fw of DMCUB may be timeout, that means it is not in idle state, such as the window frames may still be kept in cache, so reset by force will cause MMHUB hang. [HOW] After the halt command was sent, keep checking the DMCUB state until it is idle. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
hengzhou <Hengyong.Zhou@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] When enabling an HPO stream for the first time after having previously enabled a DIO stream there may be lingering DIO FIFO errors even though the DIO is no longer enabled. These can cause display clock change to hang if we don't apply the OTG disable workaround since the ramping logic is tied to OTG on. [How] The workaround wasn't being applied in the sequence of: 1 DIO stream 0 streams 1 HPO stream because current_state has no stream or planes in its context - and it's only swapped after optimize has finished. We should be using the incoming context instead to determine whether this logic is needed or not. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Leung, Martin authored
why and how: Revert this change. It was causing a black screen with certain blocks Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Sherry Wang authored
[Why] Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table, but driver will set it to default value 0x103d1110, which causes issue in some case [How] Remove the driver code, use the value set by dmub in dp_aux_init Reviewed-by:
Sherry Wang <YAO.WANG1@amd.com> Signed-off-by:
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