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  1. 18 Jul, 2017 1 commit
    • Paul Mackerras's avatar
      powerpc: Don't try to fix up misaligned load-with-reservation instructions · dda727ef
      Paul Mackerras authored
      commit 48fe9e94 upstream.
      
      In the past, there was only one load-with-reservation instruction,
      lwarx, and if a program attempted a lwarx on a misaligned address, it
      would take an alignment interrupt and the kernel handler would emulate
      it as though it was lwzx, which was not really correct, but benign since
      it is loading the right amount of data, and the lwarx should be paired
      with a stwcx. to the same address, which would also cause an alignment
      interrupt which would result in a SIGBUS being delivered to the process.
      
      We now have 5 different sizes of load-with-reservation instruction. Of
      those, lharx and ldarx cause an immediate SIGBUS by luck since their
      entries in aligninfo[] overlap instructions which were not fixed up, but
      lqarx overlaps with lhz and will be emulated as such. lbarx can never
      generate an alignment interrupt since it only operates on 1 byte.
      
      To straighten this out and fix the lqarx case, this adds code to detect
      the l[hwdq]arx instructions and return without fixing them up, resulting
      in a SIGBUS being delivered to the process.
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      [bwh: Backported to 3.2: open-code get_xop()]
      Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
      dda727ef
  2. 26 Oct, 2013 1 commit
    • Anton Blanchard's avatar
      powerpc: Handle unaligned ldbrx/stdbrx · ef9ba15d
      Anton Blanchard authored
      commit 230aef7a upstream.
      
      Normally when we haven't implemented an alignment handler for
      a load or store instruction the process will be terminated.
      
      The alignment handler uses the DSISR (or a pseudo one) to locate
      the right handler. Unfortunately ldbrx and stdbrx overlap lfs and
      stfs so we incorrectly think ldbrx is an lfs and stdbrx is an
      stfs.
      
      This bug is particularly nasty - instead of terminating the
      process we apply an incorrect fixup and continue on.
      
      With more and more overlapping instructions we should stop
      creating a pseudo DSISR and index using the instruction directly,
      but for now add a special case to catch ldbrx/stdbrx.
      Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
      ef9ba15d
  3. 02 Sep, 2010 1 commit
  4. 18 Dec, 2009 1 commit
  5. 28 Oct, 2009 1 commit
  6. 21 May, 2009 1 commit
  7. 26 Feb, 2009 1 commit
  8. 23 Feb, 2009 2 commits
  9. 13 Feb, 2009 1 commit
  10. 03 Sep, 2008 1 commit
  11. 15 Jul, 2008 1 commit
  12. 09 Jul, 2008 1 commit
  13. 01 Jul, 2008 1 commit
  14. 14 Sep, 2007 1 commit
    • Kumar Gala's avatar
      [POWERPC] Handle alignment faults on SPE load/store instructions · 26caeb2e
      Kumar Gala authored
      This adds code to handle alignment traps generated by the following
      SPE (signal processing engine) load/store instructions, by emulating
      the instruction in the kernel (as is done for other instructions that
      generate alignment traps):
      
      evldd[x]         Vector Load Double Word into Double Word [Indexed]
      evldw[x]         Vector Load Double into Two Words [Indexed]
      evldh[x]         Vector Load Double into Four Half Words [Indexed]
      evlhhesplat[x]   Vector Load Half Word into Half Words Even and Splat [Indexed]
      evlhhousplat[x]  Vector Load Half Word into Half Word Odd Unsigned and Splat [Indexed]
      evlhhossplat[x]  Vector Load Half Word into Half Word Odd Signed and Splat [Indexed]
      evlwhe[x]        Vector Load Word into Two Half Words Even [Indexed]
      evlwhou[x]       Vector Load Word into Two Half Words Odd Unsigned (zero-extended) [Indexed]
      evlwhos[x]       Vector Load Word into Two Half Words Odd Signed (with sign extension) [Indexed]
      evlwwsplat[x]    Vector Load Word into Word and Splat [Indexed]
      evlwhsplat[x]    Vector Load Word into Two Half Words and Splat [Indexed]
      evstdd[x]        Vector Store Double of Double [Indexed]
      evstdw[x]        Vector Store Double of Two Words [Indexed]
      evstdh[x]        Vector Store Double of Four Half Words [Indexed]
      evstwhe[x]       Vector Store Word of Two Half Words from Even [Indexed]
      evstwho[x]       Vector Store Word of Two Half Words from Odd [Indexed]
      evstwwe[x]       Vector Store Word of Word from Even [Indexed]
      evstwwo[x]       Vector Store Word of Word from Odd [Indexed]
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      26caeb2e
  15. 17 Aug, 2007 1 commit
    • Paul Mackerras's avatar
      [POWERPC] Handle alignment faults on new FP load/store instructions · c6d4267e
      Paul Mackerras authored
      This adds code to handle alignment traps generated by the following
      new floating-point load/store instructions, by emulating the
      instruction in the kernel (as is done for other instructions that
      generate alignment traps):
      
      lfiwax	load floating-point as integer word algebraic indexed
      stfiwx	store floating-point as integer word indexed
      lfdp	load floating-point double pair
      lfdpx	load floating-point double pair indexed
      stfdp	store floating-point double pair
      stfdpx	store floating-point double pair indexed
      
      All these except stfiwx are new in POWER6.
      
      lfdp/lfdpx/stfdp/stfdpx load and store 16 bytes of memory into an
      even/odd FP register pair.  In little-endian mode each 8-byte value is
      byte-reversed separately (i.e. not as a 16-byte unit).  lfiwax/stfiwx
      load or store the lower 4 bytes of a floating-point register from/to
      memory; lfiwax sets the upper 4 bytes of the FP register to the sign
      extension of the value loaded.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      c6d4267e
  16. 12 Apr, 2007 1 commit
  17. 09 Jun, 2006 1 commit
    • Paul Mackerras's avatar
      [PATCH] powerpc: Implement support for setting little-endian mode via prctl · fab5db97
      Paul Mackerras authored
      This adds the PowerPC part of the code to allow processes to change
      their endian mode via prctl.
      
      This also extends the alignment exception handler to be able to fix up
      alignment exceptions that occur in little-endian mode, both for
      "PowerPC" little-endian and true little-endian.
      
      We always enter signal handlers in big-endian mode -- the support for
      little-endian mode does not amount to the creation of a little-endian
      user/kernel ABI.  If the signal handler returns, the endian mode is
      restored to what it was when the signal was delivered.
      
      We have two new kernel CPU feature bits, one for PPC little-endian and
      one for true little-endian.  Most of the classic 32-bit processors
      support PPC little-endian, and this is reflected in the CPU feature
      table.  There are two corresponding feature bits reported to userland
      in the AT_HWCAP aux vector entry.
      
      This is based on an earlier patch by Anton Blanchard.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      fab5db97
  18. 18 Nov, 2005 1 commit
  19. 27 Oct, 2005 1 commit
    • David Gibson's avatar
      [PATCH] powerpc: Fix handling of fpscr on 64-bit · 25c8a78b
      David Gibson authored
      The recent merge of fpu.S broken the handling of fpscr for
      ARCH=powerpc and CONFIG_PPC64=y.  FP registers could be corrupted,
      leading to strange random application crashes.
      
      The confusion arises, because the thread_struct has (and requires) a
      64-bit area to save the fpscr, because we use load/store double
      instructions to get it in to/out of the FPU.  However, only the low
      32-bits are actually used, so we want to treat it as a 32-bit quantity
      when manipulating its bits to avoid extra load/stores on 32-bit.  This
      patch replaces the current definition with a structure of two 32-bit
      quantities (pad and val), to clarify things as much as is possible.
      The 'val' field is used when manipulating bits, the structure itself
      is used when obtaining the address for loading/unloading the value
      from the FPU.
      
      While we're at it, consolidate the 4 (!) almost identical versions of
      cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
      arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
      arch/powerpc/kernel/misc_64.S) into a single version in fpu.S.  The
      new version takes a pointer to thread_struct and applies the correct
      offset itself, rather than a pointer to the fpscr field itself, again
      to avoid confusion as to which is the correct field to use.
      
      Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
      code, which it previously did not.
      
      Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
      and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
      Booted on G5 (ARCH=powerpc) and things which previously fell over no
      longer do.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      25c8a78b
  20. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4