- 22 May, 2022 38 commits
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farah kassabri authored
Currently we're using the same poll interval value for both COMMs protocol(for sending a command and waits for an ACK) and the device CPU boot phases status waits. On COMMs protocol this interval should be much lower than the device CPU boot which may take long time to change status. Signed-off-by:
farah kassabri <fkassabri@habana.ai> Reviewed-by:
Oded Gabbay <ogabbay@kernel.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Dani Liberman authored
find_get_pid() isn't good in case the user process was run inside docker. As a result, we didn't had the PID and we couldn't kill the user process in case the device got stuck and we needed to reset the device. Signed-off-by:
Dani Liberman <dliberman@habana.ai> Reviewed-by:
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Ohad Sharabi authored
This patch let the user decide whether the translations done in the page tables will be fetched directly to the STLB right after the map. We want to let the user control whether to perform prefetch upon map operation. To do so a memory flag was added, to be used in the MAP ioctl, called HL_MEM_PREFETCH and if set- the mappings will be fetched directly to the STLB after map operation. Signed-off-by:
Ohad Sharabi <osharabi@habana.ai> Reviewed-by:
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Robin Murphy authored
Even if an IOMMU might be present for some PCI segment in the system, that doesn't necessarily mean it provides translation for the device we care about. Replace iommu_present() with a more appropriate check. Signed-off-by:
Robin Murphy <robin.murphy@arm.com> Reviewed-by:
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Moti Haimovski authored
The habanalabs HW requires memory resources to be used by its internal hardware structures. These structures are allocated and initialized by the driver. We would like to use the device HBM for that purpose. This memory is io-remapped and accessed using the writel()/writeb()/writew() commands. Since some of the HW structures are one byte in size we need to add support for the writeb() and readb() functions in the driver. Signed-off-by:
Moti Haimovski <mhaimovski@habana.ai> Reviewed-by:
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Ohad Sharabi authored
Instead of using for_each_sg when iterating sgt that contains dma entries, use the more proper for_each_sgtable_dma_sg macro. In addition, both Goya and Gaudi have the exact same implementation of the asic function that encapsulate the usage of this macro, so it is better to move that implementation to the common code. Signed-off-by:
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Rajaravi Krishna Katta authored
Use standard kernel macro to take lower 32 bits of 64-bits variable. Signed-off-by:
Rajaravi Krishna Katta <rkatta@habana.ai> Reviewed-by:
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Ohad Sharabi authored
Take advantage of the HOPs shift/masks now defined as arrays. Signed-off-by:
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Rajaravi Krishna Katta authored
Incorrect/Missing doxygen tag Signed-off-by:
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Oded Gabbay authored
As user interrupts are a common use case, this dump pollutes the dmesg log, hence removing it. Signed-off-by:
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Oded Gabbay authored
Only a hard-reset is an unexpected event which should be notify in the kernel log. Other resets are normal operations and therefore we should not pollute the log with them. Signed-off-by:
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Oded Gabbay authored
Currently we have two reset prints per reset. One is in the common code and one in each asic-specific file. We can change the asic-specific message to be debug only as we can know the type of reset being done according to the print in the common code, which is also easier to maintain. Signed-off-by:
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Oded Gabbay authored
Halting compute engines is a print that doesn't add us any information because it is always done in the reset process and not used elsewhere. Even if it was, we don't use prints to mark functions we passed through. Signed-off-by:
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Yuri Nudelman authored
During the unified memory manager release, a wrong id was used to remove an entry from the idr. Signed-off-by:
Yuri Nudelman <ynudelman@habana.ai> Reviewed-by:
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Dafna Hirschfeld authored
The debugfs memory access now uses the callback 'access_dev_mem' so there is no use of the callbacks 'debugfs_{read32,read64,write32,write6}'. Remove them. Signed-off-by:Dafna Hirschfeld <dhirschfeld@habana.ai> Reviewed-by:
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Dafna Hirschfeld authored
When accessing the configuration registers through debugfs, it is only allowed to access aligned address. Fail if address is not aligned. Signed-off-by:
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Dafna Hirschfeld authored
Currently each asic version implements 4 callbacks: 'debugfs_{read32/write32/read64/write64}' There is a lot of code duplication among the different callbacks of all asic versions. This patch unify the code in order to avoid the code duplication by iterating the pci_mem_region array in hl_device and use its fields instead of macros. Signed-off-by: -
Dafna Hirschfeld authored
This is a preparation for unifying the code of accessing device memory through debugfs. Add struct fields and callbacks that will later be used in debugfs code and will reduce code duplication among the different read{32,64}/write{32,64} callbacks of every asic. Signed-off-by: -
kernel test robot authored
drivers/misc/habanalabs/common/memory.c:2137:28: warning: symbol 'hl_ts_behavior' was not declared. Should it be static? Fixes: 4d530e7d ("habanalabs: convert ts to use unified memory manager") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Ohad Sharabi authored
When Gaudi device is secured the monitors data in the configuration space is blocked from PCI access. As we need to enable user to get sync-manager monitors registers when debugging, this patch adds a debugfs that dumps the information to a binary file (blob). When a root user will trigger the dump, the driver will send request to the f/w to fill a data structure containing dump of all monitors registers. Signed-off-by:
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Ohad Sharabi authored
The out of memory message is rephrased to more subtle expression as out of memory may be caused by the user in case of, for example, greedy allocation. In addition the user is also being notified by an error code. Signed-off-by:
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Dafna Hirschfeld authored
We currently allow accessing the whole SRAM bar size with the macro SRAM_BAR_SIZE, but the actual size of the sram region is the macro SRAM_SIZE which is only a portion of the whole bar size. So when accessing the sram through debugfs, use the macro SRAM_SIZE for the sram size which is the correct macro. Signed-off-by:
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Ohad Sharabi authored
This is necessary pre-requisite for future ASIC support, where MMU TLB prefetch is supported. Signed-off-by:
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Yuri Nudelman authored
With the introduction of the unified memory manager infrastructure, the timestamp buffers can be converted to use it. Signed-off-by:
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Yuri Nudelman authored
This is a part of overall refactoring attempt to separate nic and the core drivers. Currently, there are 4 different flows, that contain very similar code. These are the ts, nic, hwblocks and cb alloc/map flows. The similar aspect of all these flows is that they all contain a central store, with memory buffers inside, supporting the following set of operations: - Allocate buffer and return handle - Get buffer from the store with handle - Put the buffer (last put releases the buffer) - Map the buffer to the user This patch contains a generic data structure used to implement the above memory buffer store interface. Conversion of the existing code to use the new data structure will follow. Signed-off-by:
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Ofir Bitton authored
We need this property for doing backward compatibility hacks against the f/w. Signed-off-by:
Ofir Bitton <obitton@habana.ai> Reviewed-by:
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Jakob Koschel authored
To move the list iterator variable into the list_for_each_entry_*() macro in the future it should be avoided to use the list iterator variable after the loop body. To *never* use the list iterator variable after the loop it was concluded to use a separate iterator variable instead of a found boolean [1]. This removes the need to use a found variable and simply checking if the variable was set, can determine if the break/goto was hit. Link: https://lore.kernel.org/all/CAHk-=wgRr_D8CB-D9Kg-c=EHreAsk5SqXPwr9Y7k9sA6cWXJ6w@mail.gmail.com/Signed-off-by:
Jakob Koschel <jakobkoschel@gmail.com> Reviewed-by:
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Tomer Tayar authored
The required DMA mask is no longer based on input from the F/W, but it is fixed per ASIC according to its address space. As such, the per-ASIC function to get this value can be replaced with a property variable. Signed-off-by:
Tomer Tayar <ttayar@habana.ai> Reviewed-by:
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Ofir Bitton authored
When parsing firmware versions strings, driver should not assume a specific length and parse up to the maximum supported version length. Signed-off-by:
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Tomer Tayar authored
The default max power is deduced from the card type value in the CPU-CP info. This value is then set in the max power variable of the device structure. Getting the CPU-CP info is done as part of the late init phase which is called also during reset. This means that a max power value which is modified via sysfs will be reset during hard reset back to the default value. As the max power is updated in any case during device init in hl_sysfs_init(), this setting in late init can be removed, and the overriding during reset is thus avoided. Signed-off-by:
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Ofir Bitton authored
In order to allow user to have larger amount of submissions, we increase the DMA and NIC queue depth to 4K. Signed-off-by:
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Ofir Bitton authored
In order for the user to know if he can try and open device, we expose the compute ctx state. The user can now know if the context is used by another process or whether the device is still ongoing through cleanup or reset and will be available soon. Signed-off-by:
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Ofir Bitton authored
In order to be more informative during device open, we are adding a new return code -EAGAIN that indicates device is still going through resource reclaiming and hence it cannot be used yet. Signed-off-by:
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Ohad Sharabi authored
Future devices will support multiple device memory page sizes. In addition, an API for the user was added for it to be able to control the device memory allocation page size. This patch is a complementary patch to inform the user of the available page size supported by the device. Signed-off-by:
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Ohad Sharabi authored
There is no need to hold each MMU mask/shift as a denoted structure member (e.g. hop0_mask). Instead converting it to array will result in smaller and more readable code. Signed-off-by:
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Ohad Sharabi authored
This patch breaks the cumbersome implementation of "get real page size" along with it's multiple inner conditions and implement each case (according to the real complexity) inside an ASIC function. Signed-off-by:
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Ohad Sharabi authored
When using the device memory allocation API the user ought to know what is the default allocation page size. Signed-off-by:
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Ohad Sharabi authored
Looking forward we will need to report to the user what is the default page size used. This will be done more conveniently by explicitly updating the property rather than to rely on a "0 meaning default" value. Signed-off-by:
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- 20 May, 2022 1 commit
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Greg Kroah-Hartman authored
This reverts commit 6646b95a. Stephen reports that it breaks the build for him so revert it for now. Cc: Samuel Thibault <samuel.thibault@ens-lyon.org> Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Link: https://lore.kernel.org/r/20220520194637.03824f7f@canb.auug.org.auSigned-off-by:
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- 19 May, 2022 1 commit
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Greg Kroah-Hartman authored
Merge tag 'icc-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next Georgi writes: interconnect changes for 5.19 These are the interconnect changes for the 5.19-rc1 merge window consisting of driver updates. Driver changes: - New driver for SC8280XP - New driver for SDX65 - SC8180X driver fixes - Constify various data structures in that are never modified - Fix clock rate caching in RPM drivers. - Misc fixes and clean-ups Signed-off-by:
Georgi Djakov <djakov@kernel.org> * tag 'icc-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: dt-bindings: interconnect: Remove sc7180/sdx55 ipa compatibles interconnect: qcom: sc8180x: Reformat node and bcm definitions interconnect: qcom: sc8180x: Mark some BCMs keepalive interconnect: qcom: sc8180x: Fix QUP0 nodes interconnect: qcom: sc8180x: Modernize sc8180x probe dt-bindings: interconnect: Add SC8180X QUP0 virt provider interconnect: qcom: icc-rpm: Cache every clock rate interconnect: qcom: icc-rpm: Fix for cached clock rate interconnect: qcom: sc8280xp: constify qcom_icc_bcm pointers interconnect: qcom: sc8280xp: constify icc_node pointers interconnect: qcom: sc8280xp: constify qcom_icc_desc interconnect: qcom: Add SDX65 interconnect provider driver dt-bindings: interconnect: Add Qualcomm SDX65 DT bindings interconnect: qcom: constify qcom_icc_bcm pointers interconnect: qcom: constify icc_node pointers interconnect: qcom: constify qcom_icc_desc interconnect: qcom: Add SC8280XP interconnect provider dt-bindings: interconnect: qcom: Add sc8280xp binding
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