- 07 Dec, 2023 40 commits
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: 07c8ded6 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Cc: stable@vger.kernel.org # 6.2 Cc: Richard Acayan <mailingradian@gmail.com> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Acked-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20231120164331.8116-8-johan+linaro@kernel.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: b080f53a ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes") Cc: stable@vger.kernel.org # 6.5 Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: bb9efa59 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by:
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Johan Hovold authored
A recent cleanup reordering the usb_1 wakeup interrupts inadvertently switched the DP and SuperSpeed interrupt trigger types. Fixes: 4a7ffc10 ("arm64: dts: qcom: align DWC3 USB interrupts with DT schema") Cc: stable@vger.kernel.org # 5.19 Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231120164331.8116-5-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: 0b766e7f ("arm64: dts: qcom: sc7180: Add USB related nodes") Cc: stable@vger.kernel.org # 5.10 Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: de100152 ("arm64: dts: qcom: sa8775p: add USB nodes") Cc: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20231120164331.8116-3-johan+linaro@kernel.orgSigned-off-by:
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Nikita Travkin authored
Longcheer L8150 doesn't have any dedicated fuel-gauge or charger, instead making use of the pmic hardware blocks for those purposes. Add pm8916 bms and charger, as well as the battery cell description that those blocks rely on. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Nikita Travkin <nikita@trvn.ru> Link: https://lore.kernel.org/r/20231120-pm8916-dtsi-bms-lbc-v4-3-4f91056c8252@trvn.ruSigned-off-by:
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Nikita Travkin authored
pm8916 contains some hardware blocks for battery powered devices: - VM-BMS: Battery voltage monitoring block. - LBC: Linear battery charger. Add them to the pmic dtsi so the devices that make use of those blocks can enable them. Signed-off-by:
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Konrad Dybcio authored
A643 (A635 speedbin 0xac) tops out at 812 MHz. Fill in the opp-supported-hw appropriately. Note that fuseval 0xac is referred to as speedbin 1 downstream, but that was already in use upstream, so 2 was chosen instead. Signed-off-by:
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Konrad Dybcio authored
The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such, mark the GPU one as well. Fixes: 96c47197 ("arm64: dts: qcom: sc7280: Add gpu support") Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). On platforms that support it (in firmware), it is necessary to describe that link, or Adreno register access will hang the board. The current settings are functionally identical, *but* due to what is likely hardcoded security policies, the secure firmware rejects them, resulting in the board hanging. To avoid that, alter the settings such that SID 0 and 1 are described separately. Fixes: 96c47197 ("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by:
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Konrad Dybcio authored
Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU. Describe that and make sure it doesn't interfere with Chrome devices. Signed-off-by:
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Krzysztof Kozlowski authored
Add missing QDU, QRU and SDA platform names to the pattern matching all Qualcomm compatibles. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231120100617.47156-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Rohit Agarwal authored
Enable the support for USB3 controller, QMP PHY and HS PHY on SDX75 IDP. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231117080737.606687-4-quic_rohiagar@quicinc.comSigned-off-by:
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Rohit Agarwal authored
Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and HS PHY on SDX75. Signed-off-by:
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Rohit Agarwal authored
Add interconnect nodes to support interconnects on SDX75. Also parallely add the interconnect property for UART required so that the bootup to shell does not break with interconnects in place. Signed-off-by:
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Nia Espera authored
In a similar vein to https://lore.kernel.org/lkml/20220530080842.37024-3-manivannan.sadhasivam@linaro.org/, the remote processors on sm8350 fail to initialize with the 'correct' (i.e., specified in downstream) IRQ type. Change this to EDGE_RISING. Signed-off-by:
Nia Espera <nespera@igalia.com> Acked-by:
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Nia Espera authored
pmk8350 has a random tab character inserted, so remove it. Reviewed-by:
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Nia Espera authored
DMA0 node downstream is specified at 0x900000, so fix the typo. Without this, enabling any i2c node using DMA0 causes a hang. Fixes: bc08fbf4 ("arm64: dts: qcom: sm8350: Define GPI DMA engines") Fixes: 41d6bca7 ("arm64: dts: qcom: sm8350: correct DMA controller unit address") Reviewed-by:
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Nia Espera authored
Bindings for a charger controller chip found on sm8350 Signed-off-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20231111-nia-sm8350-for-upstream-v4-1-3a638b02eea5@igalia.comSigned-off-by:
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Krzysztof Kozlowski authored
SC8180x APSS Devicetree bindings expect qcom,sc8180x-apss-shared to use qcom,sdm845-apss-shared fallback: sc8180x-lenovo-flex-5g.dtb: mailbox@17c00000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,sc8180x-apss-shared'] is too short Signed-off-by: -
Krzysztof Kozlowski authored
The Samsung S6SY761 touchscreen bindings expect AVDD regulator which is missing in the Sony Xperia PDX225 DTS. There is however pinctrl setting for in the touchscreen device node with similar name: "avdd", so assume author wanted to control a fixed regulator with a GPIO. This fixes dtbs_check warning: sm6375-sony-xperia-murray-pdx225.dtb: touchscreen@48: 'avdd-supply' is a required property Signed-off-by:
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Krzysztof Kozlowski authored
Add interrupts to SM6125 DWC3 USB controller, based on downstream/vendor code of Trinket DTSI from Xiaomi Laurel device, to fix dtbs_check warnings: sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'interrupt-names' is a required property sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'oneOf' conditional failed, one must be fixed: 'interrupts' is a required property 'interrupts-extended' is a required property Signed-off-by:Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20231111164229.63803-5-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Commit 70d1e09e ("arm64: dts: qcom: sm6115: Use 64 bit addressing") converted all addresses to 64-bit addressing, but the ARMv7 memory mapped architected timer bindings expect sizes up to 32-bit. Keep 64-bit addressing but change size of memory mapping to 32-bit (size-cells=1) and adjust the ranges to match this. This fixes dtbs_check warnings like: sm6115p-lenovo-j606f.dtb: timer@f120000: #size-cells:0:0: 1 was expected Signed-off-by:
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Krzysztof Kozlowski authored
Linux handles both versions, but bindings expect GPIO properties to have 'gpios' suffix instead of 'gpio': sa8155p-adp.dtb: pci@1c00000: Unevaluated properties are not allowed ('perst-gpio' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Linux handles both versions, but bindings expect GPIO properties to have 'gpios' suffix instead of 'gpio': sc8180x-primus.dtb: pci@1c10000: Unevaluated properties are not allowed ('perst-gpio', 'wake-gpio' were unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Linux handles both versions, but bindings expect GPIO properties to have 'gpios' suffix instead of 'gpio': sc8180x-lenovo-flex-5g.dtb: pci@1c08000: Unevaluated properties are not allowed ('perst-gpio', 'wake-gpio' were unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Soundwire Devicetree bindings expect the Soundwire controller device node to be named just "soundwire": sdm845-db845c.dtb: swm@c85: $nodename:0: 'swm@c85' does not match '^soundwire(@.*)?$' Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20231111095617.16496-2-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
There is no "panic-indicator" default trigger but a property with that name: sdm845-db845c.dtb: leds: led-0: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) Fixes: 3f72e2d3 ("arm64: dts: qcom: Add Dragonboard 845c") Signed-off-by: -
Krzysztof Kozlowski authored
There is no "panic-indicator" default trigger but a property with that name: qrb5165-rb5.dtb: leds: led-user4: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) Fixes: b5cbd84e ("arm64: dts: qcom: qrb5165-rb5: Add onboard LED support") Signed-off-by:Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Bryan O'Donoghue authored
To test out a different GDSC change I wanted to have a USB keypress resume a system in suspend. Adding wakeup-source to usb_1 and usb_2 "just works" for me on rb5. Consistent with qcm2290 and sa8775p add wakeup-source to the dtsi for the SoC. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
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Steev Klimaszewski authored
The keyboard and touchpad can be used to wake the machine up from sleep, so mark them as such in the dts file. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
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Shazad Hussain authored
The volume down key is controlled by PMIC via the PON hardware on sa8775p platform, so enable the same for sa8775p-ride. Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> Link: https://lore.kernel.org/r/20231107120503.28917-1-quic_shazhuss@quicinc.comSigned-off-by:
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Krzysztof Kozlowski authored
The Qualcomm MDSS bindings expect that DPU opp-table is defined within DPU node: sm8350-hdk.dtb: display-subsystem@ae00000: Unevaluated properties are not allowed ('opp-table' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Qualcomm MDSS Embedded DisplayPort bindings do not allow sound-dai-cells: sc8280xp-lenovo-thinkpad-x13s.dtb: displayport-controller@aea0000: #sound-dai-cells: False schema does not allow [[0] Signed-off-by:
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Krzysztof Kozlowski authored
Qualcomm MDSS Embedded DisplayPort bindings do not allow sound-dai-cells: sc8180x-primus.dtb: displayport-controller@ae9a000: #sound-dai-cells: False schema does not allow [[0]] Signed-off-by:
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Krzysztof Kozlowski authored
Soundwire Devicetree bindings expect the Soundwire controller device node to be named just "soundwire": sm8250-xiaomi-elish-boe.dtb: soundwire-controller@3250000: $nodename:0: 'soundwire-controller@3250000' does not match '^soundwire(@.*)?$' Reported-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Soundwire Devicetree bindings expect the Soundwire controller device node to be named just "soundwire": sc8280xp-lenovo-thinkpad-x13s.dtb: soundwire-controller@3210000: $nodename:0: 'soundwire-controller@3210000' does not match '^soundwire(@.*)?$' Reported-by:
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Krzysztof Kozlowski authored
There is no "multi-ch-bit-off" property in LLCC, according to bindings and Linux driver: qdu1000-idp.dtb: system-cache-controller@19200000: 'multi-ch-bit-off' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Link: https://lore.kernel.org/r/20231107080417.16700-2-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
According to bindings and Linux driver there is no "multi_channel_register" address space for LLCC. The first "reg" entry is supposed to be llcc0_base since commit 43aa006e ("dt-bindings: arm: msm: Fix register regions used for LLCC banks"): qdu1000-idp.dtb: system-cache-controller@19200000: reg: [[0, 421527552, 0, 14155776], [0, 438304768, 0, 524288], [0, 572293416, 0, 4]] is too long qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:0: 'llcc0_base' was expected qdu1000-idp.dtb: system-cache-controller@19200000: reg-names: ['llcc_base', 'llcc_broadcast_base', 'multi_channel_register'] is too long Signed-off-by:
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