- 15 Jul, 2020 40 commits
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Jiansong Chen authored
Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jiansong Chen authored
since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by:
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Jiansong Chen authored
navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by:
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Jiansong Chen authored
navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by:
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Jiansong Chen authored
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Jiansong Chen authored
navy_flounder has the same mmhub IP version with sienna_cichlid, follow its setting. Signed-off-by:
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Jiansong Chen authored
since navy_flounder has the same ip offset with sienna_cichlid, follow sienna_cichlid setting for the moment. Signed-off-by:
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Jiansong Chen authored
Add soc support. Signed-off-by:
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Jiansong Chen authored
Same as navi10. Signed-off-by:
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Jiansong Chen authored
Same as navi10. Signed-off-by:
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Jiansong Chen authored
Declare the gfx/compute firmwares. Signed-off-by:
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Jiansong Chen authored
Add the asic family and IP blocks for navy flounder. Signed-off-by:
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Jiansong Chen authored
Currently navy_flounder only supports backdoor loading type. Will switch to psp load type when psp is ready. Signed-off-by:
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Jiansong Chen authored
Signed-off-by:
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Jiansong Chen authored
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Huang Rui authored
Sienna_cichlid has four sdma instances, but other chips don't. So we need expand to add multiple trap event irq id in sdma v5.2. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Jack Zhang authored
1.Skip decode_ring test in VF, because VCN in SRIOV does not support direct register read/write. 2.Skip powergating configuration in hw fini because VCN3.0 SRIOV doesn't support powergating. V2: delete unneccessary white lines and refine implementation. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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John Clements authored
resolve bug calculating fw start address within binary Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Jack Zhang authored
1.In early_init and for sriov, hardcode harvest_config=0, enc_num=1 2.sw_init/fini alloc & free mm_table for sriov doorbell setting for sriov 3.hw_init/fini Under sriov, add start_sriov to config mmsch Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings. 4.Implementation for vcn_v3_0_start_sriov V2:Clean-up some uneccessary funciton declaration. Signed-off-by:
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Jack Zhang authored
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch to set the World Switch for MM appropriately. This patch add the interface for mmsch_v3.0. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Jack Zhang authored
For gfx10 boards, except for nv12, other boards take mmio write rather than rlcg write Signed-off-by:
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Jack Zhang authored
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported. Signed-off-by:
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Evan Quan authored
Leftover of previous cleanups. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Put the common code in smu_v11_0.c instead of having one copy each. Signed-off-by:
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Evan Quan authored
This can help to maintain clear code layer. Signed-off-by:
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Evan Quan authored
As it's needed in the succeeding thermal irq setting. Signed-off-by:
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Evan Quan authored
These are needed for temp1/2/3 related hwmon interfaces. Signed-off-by:
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Evan Quan authored
These are needed for temp1/2/3 related hwmon interfaces. Signed-off-by:
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Evan Quan authored
The LCLK dpm table setup should be performed in .update_pcie_parameters(). Otherwise, the updated GenSpeed and LaneCount information will be lost. Signed-off-by:
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Evan Quan authored
This can also help to maintain clear code layer. Signed-off-by:
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Evan Quan authored
Leftover of previous performance level setting cleanups. Signed-off-by:
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Evan Quan authored
By moving the implemention to renoir_ppt.c considering it's really ASIC specific. V2: fix compile warnings below drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds] freq = table->FClocks[dpm_level].Freq; \ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); ^~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds] freq = table->FClocks[dpm_level].Freq; \ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); Signed-off-by: -
Evan Quan authored
By calling the target APIs directly. Signed-off-by:
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Evan Quan authored
Before and after setting gfx clock soft max/min frequency. Signed-off-by:
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Evan Quan authored
Use the common smu_v11_0_set_soft_freq_limited_range. Signed-off-by:
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Evan Quan authored
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by:
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Evan Quan authored
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by:
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Evan Quan authored
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by:
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Evan Quan authored
So that it can be more widely shared around SMU v11 ASICs. Signed-off-by:
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Evan Quan authored
Preparing for coming code sharing around performance level setting. Signed-off-by:
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