- 21 Aug, 2024 2 commits
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Srinivasan Shanmugam authored
This commit adds a new sysfs attribute 'enforce_isolation' to control the 'enforce_isolation' setting per GPU. The attribute can be read and written, and accepts values 0 (disabled) and 1 (enabled). When 'enforce_isolation' is enabled, reserved VMIDs are allocated for each ring. When it's disabled, the reserved VMIDs are freed. The set function locks a mutex before changing the 'enforce_isolation' flag and the VMIDs, and unlocks it afterwards. This ensures that these operations are atomic and prevents race conditions and other concurrency issues. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
This patch adds a new parameter 'enforce_isolation' to the amdgpu_job structure. This parameter is used to determine whether shader isolation should be enforced for a job. The enforce_isolation parameter is then stored in the amdgpu_job structure and used when flushing the VM. The enforce_isolation field of the amdgpu_job structure is set directly after the job is allocated This change allows more fine-grained control over shader isolation, making it possible to enforce isolation on a per-job basis rather than globally. This can be useful in scenarios where only certain jobs require isolation. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Christian König <christian.koenig@amd.com>
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- 16 Aug, 2024 38 commits
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Victor Skvortsov authored
Stop waiting for the KIQ to return back when there is a reset pending. It's quite likely that the KIQ will never response. Signed-off-by:
Lazar Lijo <Lijo.Lazar@amd.com> Tested-by:
Victor Skvortsov <victor.skvortsov@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
This commit makes enforce_isolation setting to be per GPU and per partition by adding the enforce_isolation array to the adev structure. The adev variable is set based on the global enforce_isolation module parameter during device initialization. In amdgpu_ids.c, the adev->enforce_isolation value for the current GPU is used to determine whether to enforce isolation between graphics and compute processes on that GPU. In amdgpu_ids.c, the adev->enforce_isolation value for the current GPU and partition is used to determine whether to enforce isolation between graphics and compute processes on that GPU and partition. This allows the enforce_isolation setting to be controlled individually for each GPU and each partition, which is useful in a system with multiple GPUs and partitions where different isolation settings might be desired for different GPUs and partitions. v2: fix loop in amdgpu_vmid_mgr_init() (Alex) Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Deucher authored
This commit introduces the emission of a cleaner shader at the end of the IB submission process. This is achieved by adding a new function pointer, `emit_cleaner_shader`, to the `amdgpu_ring_funcs` structure. If the `emit_cleaner_shader` function is set in the ring functions, it is called during the VM flush process. The cleaner shader is only emitted if the `enable_cleaner_shader` flag is set in the `amdgpu_device` structure. This allows the cleaner shader emission to be controlled on a per-device basis. By emitting a cleaner shader at the end of the IB submission, we can ensure that the VM state is properly cleaned up after each submission. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
The cleaner shader is used by the CP firmware to clean LDS and GPRs between processes on the CUs. This adds an internal API for GFX IP code to allocate and initialize the cleaner shader. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Deucher authored
Some chips have more than one gfxhub so check if we are a gfxhub rather than just gfxhub 0. Acked-by:
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Alex Deucher authored
The workaround seems to cause stability issues on other SDMA 5.2.x IPs. Fixes: a03ebf11 ("drm/amdgpu/sdma5.2: Update wptr registers as well as doorbell") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3556Acked-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v2_6. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v2_5. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v2_5. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v2_0. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v2_0. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v1_0. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v1_0. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v4_0_5. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v4_0. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v4_0_3. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v4_0_5. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v4_0. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v4_0_3. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v5_0. Signed-off-by:
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Alex Deucher authored
Add API for resetting user queues. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
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Alex Deucher authored
Add API for resetting user queues. Acked-by:
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Alex Deucher authored
Add API for resetting user queues. Acked-by:
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Alex Deucher authored
It will be used by the queue reset code. Acked-by:
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Alex Deucher authored
This will be used in more places in the future so add a mutex. Acked-by:
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Alex Deucher authored
Need to enter safe mode before touching GC MMIO. Acked-by:
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Alex Deucher authored
Add ring reset callback for gfx. v2: fix operator precedence (kernel test robot) Acked-by:
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Alex Deucher authored
Add ring reset callback for gfx. v2: fix operator precedence (kernel test robot) Acked-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v5_0. Signed-off-by:
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Sunil Khatri authored
Add support for logging the registers in devcoredump buffer for vcn_v3_0. Signed-off-by:
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v3_0. Signed-off-by:
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Sunil Khatri authored
Add pointer to the vcn ip dump in the vcn global structure to be accessible for all vcn version via global adev. Signed-off-by:
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Zhang Zekun authored
amdgpu_gart_table_vram_pin() and amdgpu_gart_table_vram_unpin() has been removed since commit 575e55ee ("drm/amdgpu: recover gart table at resume") remain the declarations untouched in the header files. Besides, amdgpu_dm_display_resume() has also beed removed since commit a80aa93d ("drm/amd/display: Unify dm resume sequence into a single call"). So, let's remove this unused declarations. Signed-off-by:
Zhang Zekun <zhangzekun11@huawei.com> Signed-off-by:
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Nikita Zhandarovich authored
Several cs track offsets (such as 'track->db_s_read_offset') either are initialized with or plainly take big enough values that, once shifted 8 bits left, may be hit with integer overflow if the resulting values end up going over u32 limit. Same goes for a few instances of 'surf.layer_size * mslice' multiplications that are added to 'offset' variable - they may potentially overflow as well and need to be validated properly. While some debug prints in this code section take possible overflow issues into account, simply casting to (unsigned long) may be erroneous in its own way, as depending on CPU architecture one is liable to get different results. Fix said problems by: - casting 'offset' to fixed u64 data type instead of ambiguous unsigned long. - casting one of the operands in vulnerable to integer overflow cases to u64. - adjust format specifiers in debug prints to properly represent 'offset' values. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 285484e2 ("drm/radeon: add support for evergreen/ni tiling informations v11") Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Yang Wang authored
Skip rlc firmware validation to ignore firmware header size mismatch issues. This restores the workaround added in commit 849e133c ("drm/amdgpu: Fix the null pointer when load rlc firmware") Fixes: 3af2c80a ("drm/amdgpu: refine gfx10 firmware loading") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3551Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Sunil Khatri authored
Remove ME0 registers from MI300 gfx_9_4_3 ipdump MI300 does not have gfx ME and hence those register are just empty one and could be dropped. Signed-off-by:
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Alex Deucher authored
Protect the MMIO access with safe mode. Acked-by:
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Alex Deucher authored
Protect the MMIO access with safe mode. Acked-by:
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