- 09 Nov, 2022 40 commits
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Aric Cyr authored
DC version 3.2.211 brings along the following fixes: - Wait for VBLANK during pipe programming - Adding HDMI SCDC DEVICE_ID define - Cursor update refactor: PSR-SU support condition - Update 709 gamma to 2.222 as stated in the standerd - Consider dp cable id only when data is non zero - Waiting for 1 frame to fix the flash issue on PSR1 - Update SR watermarks for DCN314 - Allow tuning DCN314 bounding box - Zeromem mypipe heap struct before using it - Use min transition for SubVP into MPO - Disable phantom OTG after enable for plane disable - Disable DRR actions during state commit - Fix fallback issues for DP LL 1.4a tests - Fix FCLK deviation and tool compile issues - Fix reg timeout in enc314_enable_fifo - Fix gpio port mapping issue - Only update link settings after successful MST link train - Enforce minimum prefetch time for low memclk on DCN32 - Set correct EOTF and Gamut flag in VRR info - Add margin for max vblank time for SubVP + DRR - Populate DP2.0 output type for DML pipe Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Asher Song authored
This reverts commit 4545ae2e. The origin patch "drm/amdgpu: getting fan speed pwm for vega10 properly" works fine. Test failure is caused by test case self. Signed-off-by:
Asher Song <Asher.Song@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Rajneesh Bhardwaj authored
amdgpu_ttm_tt_set_userptr() is also called by the KFD as part of initializing the user pages for userptr BOs and also while initializing the GPUVM for a KFD process so update the function description. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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George Shen authored
[Why] DCN3.2 DML logic uses a new output type for DP2.0, which will enable validation to pass for higher BW timings that require DP2.0 link rates. [How] Populate the DML pipe with DP2.0 output type if the signal type of the pipe_ctx is 128b/132b. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Jasdeep Dhillon <jasdeep.dhillon@amd.com> Signed-off-by:
George Shen <george.shen@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Incorporate FW delays as port of max VTOTAL calculated for SubVP + DRR cases (since it is part of the microschedule). - Also add margin for the max VTOTAL possible for SubVP + DRR cases. - Due to rounding errors in FW (integer arithmetic), the microschedule calculation can get pushed to the next frame (incorrectly) in cases where we use the max VTOTAL possible to complete the MCLK switch. - When the rounding error occurs, we are only off by 1-2 lines, use 40us margin which is working consistently. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Mike Hsieh authored
[Why] FreeSync always use G2.2 EOTF and Native gamut [How] Set EOTF and Gamut flags accordingly Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Mike Hsieh <Mike.Hsieh@amd.com> Tested-by:
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Dillon Varone authored
[WHY?] Data return times when using lowest memclk can be <= 60us, which can cause underflow on high bandwidth displays with a workload. [HOW?] Enforce a minimum prefetch time during validation for low memclk modes. Reviewed-by:
Dillon Varone <Dillon.Varone@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Currently driver reduces verified link caps on DPIA devices if a link is trained at a link rate below the max rate verified during link detection. This blocks high bandwidth modes after setting a low bandwidth mode. [HOW] Only update link rate after a successful link train if link is MST. Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Steve Su authored
[Why] 1. Port of gpio has different mapping. [How] 1. Add a dummy entry in mapping table. 2. Fix incorrect mask bit field access. Reviewed-by:
Steve Su <steve.su@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] The link enablement sequence can end up resetting the encoder while the PHY symclk isn't yet on. This means that waiting for symclk on will timeout, along with the reset bit never asserting high. This causes unnecessary delay when enabling the link and produces a warning affecting multiple IGT tests. [How] Don't wait for the symclk to be on here because firmware already does. Don't wait for reset if we know the symclk isn't on. Split the reset into a helper function that checks the bit and decides whether or not a delay is sufficient. Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Chaitanya Dhere authored
[Why] Recent backports from open source do not have header inclusion pattern that is consistent with inclusion style in the rest of the file. This breaks the internal tool builds as well. A recent commit erronously modified the original DML formula for calculating ActiveClockChangeLatencyHidingY. This resulted in a FCLK deviation from the golden values. [How] Change the way in which display_mode_vba.h is included so that it is consistent with the inclusion style in rest of the file which also fixes the tool build. Restore the DML formula to its original state to fix the FCLK deviation. Reviewed-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Tested-by:
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Mustapha Ghaddar authored
[WHY] Unlike DP or USBC, the USB4 link does not get its own encoder and has to share therefore verify_caps is skipped. [HOW] Fix the fallback logic for automated tests and take that into consideration for LT and LS. Reviewed-by:
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Wesley Chalmers authored
[WHY] Committing a state while performing DRR actions can cause underflow. [HOW] Disabled features performing DRR actions during state commit. Need to follow-up on why DRR actions affect state commit. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Need to disable phantom OTG after it's enabled in order to restore it to it's original state. - If it's enabled and then an MCLK switch comes in we may not prefetch the correct data since the phantom OTG could already be in the middle of the frame. Reviewed-by:
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Alvin Lee authored
[Description] - For SubVP transitioning into MPO, we want to use a minimal transition to prevent transient underflow - Transitioning a phantom pipe directly into a "real" pipe can result in underflow due to the HUBP still having it's "phantom" programming when HUBP is unblanked (have to wait for next VUPDATE of the new OTG) - Also ensure subvp pipe lock is acquired early enough for programming in dc_commit_state_no_check - When disabling phantom planes, enable phantom OTG first so the disable gets the double buffer update Reviewed-by:
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Aurabindo Pillai authored
[Why&How] Bug was caused when moving variable from stack to heap because it was reusable and garbage was left over, so we need to zero mem. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] We're missing the helpers from dcn20 that would allow overriding these with DC debug options. [How] Use dcn20_patch_bounding_box to support overriding all the relevant values. Reviewed-by:
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Nicholas Kazlauskas authored
[Why & How] New values requested by hardware after fine-tuning. Update for all memory types. Reviewed-by:
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Ryan Lin authored
[Why] Needs more frames waiting before the PSR_Exit sending for the specific TCON. [How] Add relock_delay_frame_cnt to control how many frames waiting are needed before the PSR_Exit sending. The default value is 0. The Driver side can set this variable for specific TCONs. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Ryan Lin <tsung-hua.lin@amd.com> Tested-by:
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Wenjing Liu authored
Cable ID is a DP2 feature to identify max certified link rate that a cable can carry. The cable identification method requires both cable and display hardware support. Since the specs comes late, it is anticipated that the first round of DP2 cables and displays may not be fully compatible to reliably return cable ID data. Therefore the decision of our cable id policy is that if the cable can return non zero cable id data, we will take cable's link rate capability into account. However if we get zero data, the cable link rate capability is considered inconclusive. In this case, we will not take cable's capability into account to avoid of over limiting hardware capability from users. The max overall link rate capability is still determined after actual dp pre-training. Cable id is considered as an auxiliary method of determining max link bandwidth capability. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Nawwar Ali authored
[WHY] Previously driver use gamma 2.2 for 709 color space, but the standard is to use gamma of 2.222 [HOW] Change it gamma to 2.222 Reviewed-by:Nawwar Ali <nawwar.ali@amd.com> Tested-by:
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Max Tseng authored
[Why] PSR-SU requires extra conditions while cursor update. Reviewed-by:
Max Tseng <Max.Tseng@amd.com> Tested-by:
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Leo Ma authored
[Why && How] We will need to differentiate vendor behavior in the future. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Leo Ma <hanghong.ma@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Wait for vblank during front end programming for global sync to ensure all double buffer updates take. - This prevents underflow in some cases. Reviewed-by:
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Christian König authored
It can happen that we query the sequence value before the callback had a chance to run. Workaround that by grabbing the fence lock and releasing it again. Should be replaced by hw handling soon. Signed-off-by:
Christian König <christian.koenig@amd.com> CC: stable@vger.kernel.org # 5.19+ Fixes: 5255e146 ("drm/amdgpu: rework TLB flushing") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2113Acked-by:
Philip Yang <Philip.Yang@amd.com> Tested-by:
Stefan Springer <stefanspr94@gmail.com> Signed-off-by:
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Felix Kuehling authored
Checkpoint BOs last. That way we don't need to close dmabuf FDs if something else fails later. This avoids problematic access to user mode memory in the error handling code path. criu_checkpoint_bos has its own error handling and cleanup that does not depend on access to user memory. In the private data, keep BOs before the remaining objects. This is necessary to restore things in the correct order as restoring events depends on the events-page BO being restored first. Fixes: be072b06 ("drm/amdkfd: CRIU export BOs as prime dmabuf objects") Reported-by:
Jann Horn <jannh@google.com> CC: Rajneesh Bhardwaj <Rajneesh.Bhardwaj@amd.com> Signed-off-by:
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Felix Kuehling authored
mutex_unlock before the exit label because all the error code paths that jump there didn't take that lock. This fixes unbalanced locking errors in case of restore errors. Fixes: 40e8a766 ("drm/amdkfd: CRIU checkpoint and restore events") Signed-off-by:
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Tim Huang authored
Some of the unused messages that were used earlier in development have been freed up as spare messages, no intended functional changes. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Tim Huang <tim.huang@amd.com> Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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https://gitlab.freedesktop.org/skeggsb/nouveauDave Airlie authored
This is the pull request for a whole bunch of fixes and prep-work that was done to support Ampere acceleration prior to GSP-RM being available. It uses the ACR firmware released by NVIDIA in linux-firmware, as we do on earlier GPUs. The work to support running on top of GSP-RM also heavily depends on various pieces of this series. In addition to the new HW support, general stability of the driver should be improved, especially around recovering HW from bugs that can be generated by userspace driver components. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Ben Skeggs <bskeggs@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/CABDvA==s+nZD0n7CuRWLPE=Pj+02CN13r+ZQJxoHQ_EmR+o=XQ@mail.gmail.com
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Ben Skeggs authored
v2: - whitespace Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Gourav Samaiya <gsamaiya@nvidia.com>
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Ben Skeggs authored
v2. fixup for ga103 early merge Signed-off-by:
Lyude Paul <lyude@redhat.com>
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Ben Skeggs authored
v2. fixup for ga103 early merge Signed-off-by:
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Ben Skeggs authored
v2. fixup for ga103 early merge Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
We weren't sending the high bits, though they're zero currently anyway. Signed-off-by:
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Ben Skeggs authored
NVIDIA provided this on Turing, but we kept using the hardcoded version from Volta (where they didn't). Switch to the firmware version prior to Ampere. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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Ben Skeggs authored
Match RM. Signed-off-by:
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