- 02 Feb, 2021 4 commits
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xinhui pan authored
Flag TTM_PL_FLAG_CONTIGUOUS is only valid for VRAM domain. So fix the false positive by checking memory type too. Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ramesh Errabolu authored
drm/amdgpu: Limit the maximum size of contiguous VRAM that can be encapsulated by an instance of DRM memory node [Why] Enable 1:1 mapping between VRAM of a DRM node and a scatterlist node [How] Ensure construction of DRM node to not exceed specified limit Reviewed-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
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Huang Rui authored
In drm_gem_object_free, it will call funcs of drm buffer obj. So kfd_alloc should use amdgpu_gem_object_create instead of amdgpu_bo_create to initialize the funcs as amdgpu_gem_object_funcs. [ 396.231390] amdgpu: Release VA 0x7f76b4ada000 - 0x7f76b4add000 [ 396.231394] amdgpu: remove VA 0x7f76b4ada000 - 0x7f76b4add000 in entry 0000000085c24a47 [ 396.231408] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 396.231445] #PF: supervisor read access in kernel mode [ 396.231466] #PF: error_code(0x0000) - not-present page [ 396.231484] PGD 0 P4D 0 [ 396.231495] Oops: 0000 [#1] SMP NOPTI [ 396.231509] CPU: 7 PID: 1352 Comm: clinfo Tainted: G OE 5.11.0-rc2-custom #1 [ 396.231537] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS WCD0401N_Weekly_20_04_0 04/01/2020 [ 396.231563] RIP: 0010:drm_gem_object_free+0xc/0x22 [drm] [ 396.231606] Code: eb ec 48 89 c3 eb e7 0f 1f 44 00 00 55 48 89 e5 48 8b bf 00 06 00 00 e8 72 0d 01 00 5d c3 0f 1f 44 00 00 48 8b 87 40 01 00 00 <48> 8b 00 48 85 c0 74 0b 55 48 89 e5 e8 54 37 7c db 5d c3 0f 0b c3 [ 396.231666] RSP: 0018:ffffb4704177fcf8 EFLAGS: 00010246 [ 396.231686] RAX: 0000000000000000 RBX: ffff993a0d0cc400 RCX: 0000000000003113 [ 396.231711] RDX: 0000000000000001 RSI: e9cda7a5d0791c6d RDI: ffff993a333a9058 [ 396.231736] RBP: ffffb4704177fdd0 R08: ffff993a03855858 R09: 0000000000000000 [ 396.231761] R10: ffff993a0d1f7158 R11: 0000000000000001 R12: 0000000000000000 [ 396.231785] R13: ffff993a0d0cc428 R14: 0000000000003000 R15: ffffb4704177fde0 [ 396.231811] FS: 00007f76b5730740(0000) GS:ffff993b275c0000(0000) knlGS:0000000000000000 [ 396.231840] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 396.231860] CR2: 0000000000000000 CR3: 000000016d2e2000 CR4: 0000000000350ee0 [ 396.231885] Call Trace: [ 396.231897] ? amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x24c/0x25f [amdgpu] [ 396.232056] ? __dynamic_dev_dbg+0xcd/0x100 [ 396.232076] kfd_ioctl_free_memory_of_gpu+0x91/0x102 [amdgpu] [ 396.232214] kfd_ioctl+0x211/0x35b [amdgpu] [ 396.232341] ? kfd_ioctl_get_queue_wave_state+0x52/0x52 [amdgpu] Fixes: 246cb7e4 ("drm/amdgpu: Introduce GEM object functions") Reviewed-by:
Changfeng <changzhu@amd.com> Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Huang Rui authored
We cannot modify initial_domain every time while the retry starts. That will cause the busy waiting that unable to switch to GTT while the vram is not enough. Fixes: f8aab604 ("drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs") Signed-off-by:
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- 01 Feb, 2021 7 commits
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Alex Deucher authored
On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Both interfaces work properly on the boards I have. Let's try and use the percent interface instead. v2: rebase on revert Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408 Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by:
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Alex Deucher authored
On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Revert this for now to fix 5.10, 5.11. The follow on patch fixes this properly for 5.12. This reverts commit 8d6e65ad. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408Signed-off-by:
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Abaci Team authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:3137:35-40: WARNING: conversion to bool not needed here Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Suggested-by:
Yang Li <oswb@linux.alibaba.com> Signed-off-by:
Abaci Team <abaci-bugfix@linux.alibaba.com> Signed-off-by:
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Ori Messinger authored
The purpose of this patch is to add a missing device ID for Sienna Cichlid. The missing ID "0x73A1" is now added to the "amdgpu_drv.c" file. Signed-off-by:
Ori Messinger <Ori.Messinger@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Evan Quan authored
Supplement of previous fix. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Matt Coffin authored
Currently, the the input to the pp_od_clk_voltage sysfs interface has two adjacent separator characters, i.e. "\n\0", then we try to parse an argument out of the empty string, whereas we really should just ignore this case, and treat any number of adjacent separators as one separator for arguments. We do this here by simply skipping the argument parsing for all empy-string arguments. An example test case would be `echo 's 1 900' > pp_od_clk_voltage` (note the two spaces after the 's'. This also solves the issue where the written string ends with both a newline, and a nul-terminator, '\n\0', as is the case for `echo 's 1 900' > pp_od_clk_voltage` since the recent rebase. Got lost during code rebase/merge. No need to port this to other branches. Reviewed-by:
Matt Coffin <mcoffin13@gmail.com> Signed-off-by:
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Evan Quan authored
This reverts commit 2456c290. Got lost during code rebase/merge. No need to port this to other branches. Signed-off-by:
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- 28 Jan, 2021 2 commits
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Lang Yu authored
Move all the dummy functions in amdgpu_amdkfd.c to amdgpu_amdkfd.h as inline functions. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Suggested-by:
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Alex Deucher authored
Until the issues in the SMU firmware are fixed. Signed-off-by:
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- 25 Jan, 2021 12 commits
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Mario Kleiner authored
This fixes corrupted display output in HDMI deep color 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3. It will hopefully also provide fixes for other DCE's up to DCE-11, assuming those will need similar fixes, but i could not test that for HDMI due to lack of suitable hw, so viewer discretion is advised. dce110_stream_encoder_hdmi_set_stream_attribute() is used for HDMI setup on all DCE's and is missing color_depth assignment. dce110_program_pix_clk() is used for pixel clock setup on HDMI for DCE 6-11, and is missing color_depth assignment. Additionally some of the underlying Atombios specific encoder and pixelclock setup functions are missing code which is in the classic amdgpu kms modesetting path and the in the radeon kms driver for DCE6/DCE8. encoder_control_digx_v3() - Was missing setup code wrt. amdgpu and radeon kms classic drivers. Added here, but untested due to lack of suitable test hw. encoder_control_digx_v4() - Added missing setup code. Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color output at 10 bpc and 12 bpc. Note that encoder_control_digx_v5() has proper setup code in place and is used, e.g., by DCE-11.2, but this code wasn't used for deep color setup due to the missing cntl.color_depth setup in the calling function for HDMI. set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon kms. Added here, but untested due to lack of hw. set_pixel_clock_v6() - Missing setup code added. Successfully tested on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI deep color output with 10 bpc or 12 bpc. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Mario Kleiner authored
In set_clamp(), the comments and definitions for the COLOR_DEPTH_101010 and COLOR_DEPTH_121212 cases directly contradict the code comment which explains how this should work, whereas the COLOR_DEPTH_888 case is consistent with the code comments. Comment says the bitmask should be chosen to align to the top-most 10 or 12 MSB's on a 14 bit bus, but the implementation contradicts that: 10 bit case sets a mask for 12 bpc clamping, whereas 12 bit case sets a mask for 14 bpc clamping. Note that during my limited testing on DCE-8.3 (HDMI deep color) and DCE-11.2 (DP deep color), this didn't have any obvious ill effects, neither did fixing it change anything obvious for the better, so this fix may be inconsequential on DCE, and just reduce the confusion of innocent bystanders when reading the code and trying to investigate problems with 10 bpc+ output. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by:
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Arnd Bergmann authored
clang warns about the -mhard-float command line arguments on architectures that do not support this: clang: error: argument unused during compilation: '-mhard-float' [-Werror,-Wunused-command-line-argument] Move this into the gcc-specific arguments. Fixes: e77165bf ("drm/amd/display: Add DCN3 blocks to Makefile") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Dan Carpenter authored
The debug printk dereferences "link->link_enc" before we have ensured that it is non-NULL. Fix this potential NULL derefence by moving the printk after the check. Fixes: 64ff0882 ("drm/amd/display: Log link/connector info provided in BIOS object table") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Jonathan Gray authored
Change the license of color_table.c to match color_table.h granting permission to modify and distribute. Signed-off-by:
Jonathan Gray <jsg@jsg.id.au> Signed-off-by:
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Colin Ian King authored
Currently the ! operator is incorrectly being used to flip bits on mask values. Fix this by using the bit-wise ~ operator instead. Addresses-Coverity: ("Logical vs. bitwise operator") Fixes: 3c9a7b7d ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") Reviewed-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Arunpravin authored
store swsmu user power configurations which include power limit, clock frequencies, fan speed and fan mode on suspend and reinstate on resume. V2: Addressed Lijo's review comments added a function to set clock interdependencies add check on fan control mode to reapply fan speed V3: Addressed review comments from Alex moved store logic and reinstate function call into swSMU V4: added a logic to keep off storing configurations in suspend V5: Addressed review comments from Lijo add a restore flag give restore priority to mclk comparing fclk and socclk Signed-off-by:Arunpravin <Arunpravin.PaneerSelvam@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Jingwen Chen authored
[Why] when vram lost happened in guest, try to write vram can lead to kernel stuck. [How] When the readback data is invalid, don't do write work, directly reschedule a new work. Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by:
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Lang Yu authored
Replace "/" with div_u64 for 32-bit OS. On 32-bit OS, the use of "/" for 64-bit division will cause build error, i.e. "__udivdi3/__divdi3 undefined!". Fixes: ea7154d8 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code") Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Pratik Vishwakarma authored
This reverts commit 57eeaf47. Original issue of flash line when MPO enabled on idle screen was fixed by raising clocks. This had negative effect of extra power being drained. With the upstream commit 9d03bb10 ("drm/amd/display: disable dcn10 pipe split by default") flash line issue was fixed and had positive effect for battery life. Hence this patch is no more required. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Horace Chen authored
Fix a racing issue when jobs on 2 rings timeout simultaneously. If 2 rings timed out at the same time, the amdgpu_device_gpu_recover will be reentered. Then the adev->gmc.xgmi.head will be grabbed by 2 local linked list, which may cause wild pointer issue in iterating. lock the device earily to prevent the node be added to 2 different lists. also increase karma for the skipped job since the job is also timed out and should be guilty. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Felix Kuehling authored
Enable pinning of VRAM without forcing it to be contiguous. When memory is already pinned, make sure it's contiguous if requested. Suggested-by:
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- 21 Jan, 2021 13 commits
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Huang Rui authored
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Felix Kuehling authored
ROCm user mode depends on userptr support. Without it, KFD is basically useless. Make sure HSA_AMD selects the same options as DRM_AMDGPU_USERPTR to avoid broken configurations where userptr gets enabled but its dependencies are disabled. Signed-off-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
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Huang Rui authored
This patch is to help firmware designer to know the smc message timeout status. Signed-off-by:
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Feifei Xu authored
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Acked-by:
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Jinzhou Su authored
Send allow GfxOff message to SMU to enter GfxOff mode as default. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
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Jiapeng Zhong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 1009:6-16: WARNING: Assignment of 0/1 to bool variable. ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 200:2-10: WARNING: Assignment of 0/1 to bool variable. Reviewed-by:
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Colin Ian King authored
There are two spelling mistakes of the function name, fix this by using __func__ instead of a hard coded name string. Reviewed-by:
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Bhawanpreet Lakha authored
Update the function for idle optimizations -remove hardcoded size -enable no memory-request case -add cursor copy -update mall eligibility check case Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
-Uncomment watermark set d -This populates the wm table so that it can be sent to PMFW -This watermark table is used when we are in mall stutter Signed-off-by:
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Aaron Liu authored
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Acked-by:
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Jinzhou Su authored
Driver should enable the CGPG feature for RLC in safe mode to prevent any misalignment or conflict in middle of any power feature entry/exit sequence. Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1, and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value in refclk count. Reviewed-by:
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Prike Liang authored
In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL. Signed-off-by:
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- 20 Jan, 2021 2 commits
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Jinzhou Su authored
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by:
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Jinzhou Su authored
1. Remove PP_GFXOFF_MASK and then GFXOFF can be enabled by user space. 2. GFXOFF is still disabled on Vangogh by default. 3. When GFXOFF feature on Vangogh landed, will enable GFXOFF by default. 4. GFXOFF can be enabled by debugfs interface amdgpu_gfxoff. Signed-off-by:
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