Commits · e26c9d80b830812b0fd4dc02cb9a6ac21ddc3bb0 · Kirill Smelkov / linux

16 Nov, 2020 17 commits

drm/amd/display: set dpp dto as per requested clk for lower case. · e26c9d80

Yongqiang Sun authored Nov 04, 2020

[Why]
Blue screen when PNP with multiple monitor or hotplug external monitor when playing video
due to dpp dto isn't programmed properly.
If lower dpp clock, dpp dto need to be programmed first, and actual dpp clk not avalable yet.

[How]
set dpp dto as per request clk for lower case before dpp clk update, and after dpp clk updated
set dpp dto again with actual dpp clk.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

e26c9d80

drm/amd/display: Add I2C memory low power support · af435e3f

Jacky Liao authored Oct 27, 2020

[Why]
The I2C memory blocks should be powered down when they are not in use.
This will reduce power consumption.

[How]
1. Write to I2C_LIGHT_SLEEP_FORCE to put memory in light sleep when
   released
2. Added a debug option to allow this behaviour to be turned off
Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

af435e3f

drm/amd/display: Detect dynamic backlight support in eDP sink · 65e870df

Roy Chan authored Oct 30, 2020

[Why]
Check if the eDP sink supports the dynamic backlight control

[How]
Query the dynamic backlight capability in DPCD (eDP case only)
Signed-off-by: Roy Chan <roy.chan@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

65e870df

drm/amd/display: minor restructuring of pbn calculation functions · 786b4061

Wenjing Liu authored Oct 06, 2020

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

786b4061

drm/amd/display: fix cursor calculation for 1xnY rotated display groups · aceeeea3

Samson Tam authored Oct 30, 2020

[Why]
Cursor is missing on displays 2 and up when doing rotated
 display groups in 1xnY setup.  Calculation puts cursor
 out of bounds so it is not enabled.

[How]
In dcn10_set_cursor_position(), add in viewport.y into cursor
 calculations for 1xnY rotated display groups.
For pipe split, check viewport.y for both pipes and use lower one
 to normalize cursor position before calculations.
Add odm 2:1 support ( using same calculations as pipe split ).
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

aceeeea3

drm/amd/display: remove unused dml variables · 89c5ca3b

Dmytro Laktyushkin authored Aug 27, 2020

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

89c5ca3b

drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 · 157cc885

Sung Lee authored Nov 02, 2020

[WHY & HOW]
Currently if VBIOSSMC_Result_UnknownCmd is returned as result of smu msg
there is no way to know.  Put 1 in param so if 1 is returned, this unknown case is handled.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

157cc885

drm/amd/display: Populate hostvm parameter before DML calculation · 82df77ae

Sung Lee authored Oct 30, 2020

[Why]
If the system does not have hostvm enabled, disabling it for
DML validation will allow more modes to pass at lower voltage
levels.

[How]
When initializing HostVM save state to hubbub and read back
when populating DML pipes from context.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

82df77ae

drm/amd/display: Hook up PSR residency command to DSAT · b8e0b3d6

Wyatt Wood authored Oct 21, 2020

[Why]
Use GPINT command to get PSR residency from FW.

[How]
Hook up PSR residency command to DSAT.
Since PSR Count Request is deprecated, we will use this.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b8e0b3d6

drm/amd/display: Program dpp dto based on actual dpp clk · 58cae8ac

Yongqiang Sun authored Nov 02, 2020

[Why]
dpp dto phase and modulo are programmed with actual dpp global clk
and pipe clk. Need to use actual dpp clk to prgoram dpp dto modulo
to get more accuracy ratio.

[How]
assign actual dpp clk to dccg for dpp modulo programming.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

58cae8ac

drm/amdgpu/sriov: reopen sienna_child smu ip block under sriov · acf2740f

Jane Jian authored Oct 16, 2020

open smu ip block meets with one-vf mode need
Signed-off-by: Jane Jian <Jane.Jian@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

acf2740f

drm/amdgpu: update golden setting for sienna_cichlid · 94d52a35

Likun Gao authored Nov 16, 2020

Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

94d52a35

drm/amd/pm: update driver if file for sienna cichlid · 34d903d1

Likun Gao authored Nov 16, 2020

Update driver if file for sienna cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

34d903d1

drm/amd/pm: enable the fine grain tuning function for vangogh · 93a80241

Xiaojian Du authored Nov 12, 2020

This patch is to enale the fine grain tuning function for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

93a80241

drm/amd/pm: add the fine grain tuning function for vangogh · c98ee897

Xiaojian Du authored Nov 12, 2020

This patch is to add the fine grain tuning function for vangogh.
This function uses the pp_od_clk_voltage sysfs file to configure the min
and max value of gfx clock frequency or restore the default value.

Command guide:
echo "s level value" > pp_od_clk_voltage
        "s" - set the sclk frequency
        "level" - 0 or 1, "0" represents the min value,  "1" represents
        the max value
        "value" - the target value of sclk frequency, it should be
        limited in the safe range
echo "r" > pp_od_clk_voltage
	"r" - reset the sclk frequency, restore the default value
        instantly
echo "c" > pp_od_clk_voltage
        "c" - commit the min and max value of sclk frequency to the system
        only after the commit command, the setting target values by "s" command
        will take effect.
Example:
1)check the default sclk frequency
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0:        200Mhz
	1:       1400Mhz
	OD_RANGE:
	SCLK:     200MHz       1400MHz
2)use "s" -- set command to configure the min or max sclk frequency
	$ echo "s 0 600" > pp_od_clk_voltage
	$ echo "s 1 1000" > pp_od_clk_voltage
	$ echo "c" > pp_od_clk_voltage
        $ cat pp_od_clk_voltage
	OD_SCLK:
	0:        600Mhz
	1:       1000Mhz
	OD_RANGE:
	SCLK:     200MHz       1400MHz
3)use "r" -- reset command to restore the min and max sclk frequency
	$ echo "r" > pp_od_clk_voltage
        $ cat pp_od_clk_voltage
	OD_SCLK:
	0:        200Mhz
	1:       1400Mhz
	OD_RANGE:
	SCLK:     200MHz       1400MHz
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

c98ee897

drm/amd/display: Update dmub code · 5fe6b98a

Bhawanpreet Lakha authored Nov 13, 2020

There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5fe6b98a

drm/amdgpu: fix usable gart size calculation · b3fcde18

Nirmoy Das authored Nov 12, 2020

amdgpu_do_test_moves() is failing because of wrong
usable gart size calculation and throwing:

[drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 0000000020bdc9f3 bind failed
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b3fcde18

13 Nov, 2020 23 commits

drm/amd/display: Extract 3rd plane from metadata · 1331e630

Bas Nieuwenhuizen authored Nov 11, 2020

Now that we actually expose the right number of planes we get
problems with modifier aware libva if we use an unsupported modifier.

So this ensures that we as much as possible use a modifier that
radeonsi can actually render to without going to extreme difficulty
to synchronize an extra DCC metadata plane with implicit sync.

Looking into the opaque metadata isn't ideal but this converts to
something mainly for the purpose of the userspace driver and falls
back properly if it isn't what we expect.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1331e630

drm/amd/display: Set new format info for converted metadata. · 816853f9

Bas Nieuwenhuizen authored Nov 11, 2020

If we use DCC modifiers this can increase the number of planes from
the initial 1 plane with metadata, so that we get a valid modifier
from getfb2.

Since the code didn't update the format_info getfb2 would only ever
return 1 plane with a modifier for which userspace expects > 1.

This moves the format lookup to amdgpu_display.c so we do not have
issues when DC is not compiled.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

816853f9

drm/amd/display: Store gem objects for planes 1-3 · 3505b2ff

Bas Nieuwenhuizen authored Nov 11, 2020

Also do the proper validation which was missed.

Besides the missing validation, not storing the objects in the
framebuffer led to wrong results in the getfb2 ioctl.

Note that this should really have been done for multi-plane
formats like NV12 already before modifiers landed.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3505b2ff

drm/fourcc: add table describing AMD modifiers bit layout · 544645f2

Simon Ser authored Nov 13, 2020

The table describes how each bit in the u64 value is used. Explicitly
state which values a field can take if we have defines for them. Also
add a note when a field isn't always populated.

Forcing people to update the table when changing the bit layout should
make it more obvious when there's a mistake, I hope.

If we get to the point where the bit layout gets more complicated, it
might be worth it to split the table into multiple tables (e.g. one for
GFX8, one for GFX9+, and so on).
Signed-off-by: Simon Ser <contact@emersion.fr>
Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

544645f2

drm/fourcc: Fix modifier field mask for AMD modifiers. · b7397bad

Bas Nieuwenhuizen authored Nov 13, 2020

The DCC_MAX_COMPRESSED_BLOCK has to contain one of
AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
fit in 1 bit.

Fix this cleanly while it is only in drm-next.

Fixes: 8ba16d59 ("drm/fourcc: Add AMD DRM modifiers.")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b7397bad

drm/amd/display: Add missing pflip irq for dcn2.0 · 52f6f16d

Alex Deucher authored Nov 13, 2020

If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

52f6f16d