- 13 Mar, 2018 23 commits
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Finn Thain authored
In jazz_esp and sun3x_esp, the esp_driver_ops methods pass esp->dev in dma api calls as if it was a pointer to a struct device. But it actually points to a struct platform_device. Fix this. Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by:
Finn Thain <fthain@telegraphics.com.au> Reviewed-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by:
Martin K. Petersen <martin.petersen@oracle.com>
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Xiang Chen authored
Export device table of v3 hw to userspace, or auto probe will fail for v3 hw. Also change the module alias to include "pci", instead of "platform". Signed-off-by:
Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by:
John Garry <john.garry@huawei.com> Signed-off-by:
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Xiaofei Tan authored
Do some modifications for register configuring for hip08. In future, to reduce kernel churn with patches to modify registers, any registers which may change between board models (mostly PHY/SERDES related) should be set in ACPI reset handler. Signed-off-by:
Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by:
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Xiang Chen authored
The patch does some code cleanup and fixes some small bugs: - Correct return status of phy_up_v3_hw() and phy_bcast_v3_hw() - Add static for function phy_get_max_linkrate_v3_hw() - Change exception return status when no reset method - Change magic value to ts->stat in slot_complete_vx_hw() - Remove unnecessary check for dev_is_sata() - Fix some issues of alignment and indents (Authored by Xiaofei Tan in another patch, but added here to be practical) Signed-off-by:
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Xiaofei Tan authored
It is an implicit regulation that error code that function returned should be negative. But hisi_sas_task_prep() doesn't follow this. This may cause problems in the upper layer code. For example, in sas_expander.c of libsas, smp_execute_task_sg() may return the number of bytes of underrun. It will be conflicted with the scenaio lldd_execute_task() return an positive error code. This patch change the return value from SAS_PHY_DOWN to -ECOMM in hisi_sas_task_prep(). Signed-off-by:
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Xiang Chen authored
The structure element hisi_sas_devices.running_req to count how many commands are active is in effect only ever written in the code, so remove it. Signed-off-by:
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Xiaofei Tan authored
The current 110ms expiry time is not long enough for the internal abort task. The reason is that the internal abort task could be blocked in HW if the HW is retrying to set up link. The internal abort task will be executed only when the retry process finished. The maximum time is 5s for the retry of setting up link. So, the timer expire should be more than 5s. This patch increases it from 110ms to 6s. Signed-off-by:
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Xiaofei Tan authored
It is not right to set the register PROG_PHY_LINK_RATE while PHY is still enabled. So if we want to change PHY linkrate, we need to disable PHY before setting the register PROG_PHY_LINK_RATE, and then start-up PHY. This patch is to fix this issue. Signed-off-by:
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Xiaofei Tan authored
In sysfs, there are two files about minimum linkrate, and also two files for maximum linkrate. Take maximum linkrate example, maximum_linkrate_hw is read-only and indicated by the register HARD_PHY_LINKRATE, and maximum_linkrate is read-write and corresponding to the register PROG_PHY_LINK_RATE. But in the function phy_up_v*_hw(), we get *_linkrate value from HARD_PHY_LINKRATE. It is not right. This patch is to fix this issue. Unreferenced PHY-interrupt enum is also removed for v3 hw. Signed-off-by:
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Xiaofei Tan authored
The register SAS_PHY_CTRL is configured according to signal quality. The signal quality is calculated by signal attenuation of hardware physical link. It may be different for different PCB layout. So, in order to give better support to new board, this patch add support to reading the devicetree property, "hisilicon,signal-attenuation". Of course, we still keep an default value in driver to adapt old board. Signed-off-by:
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Xiaofei Tan authored
For some new boards with hip07 chipset we are required to set PHY config registers differently. The hw property which determines how to set these registers is in the PHY signal attenuation readings. This patch add an devicetree property, "hisilicon,signal-attenuation", which is used to describe the signal attenuation of an board. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Douglas Gilbert authored
The SCSI PRE-FETCH (10 or 16) command is present both on hard disks and some SSDs. It is useful when the address of the next block(s) to be read is known but it is not following the LBA of the current READ (so read-ahead won't help). It returns two "good" SCSI Status values. If the requested blocks have fitted (or will most likely fit (when the IMMED bit is set)) into the disk's cache, it returns CONDITION MET. If it didn't (or will not) fit then it returns GOOD status. The goal of this patch is to stop the SCSI subsystem treating the CONDITION MET SCSI status as an error. The current state makes the PRE-FETCH command effectively unusable via pass-throughs. Signed-off-by:
Douglas Gilbert <dgilbert@interlog.com> Reviewed-by:
Bart Van Assche <bart.vanassche@wdc.com> Signed-off-by:
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James Smart authored
Updated Copyright in files updated as part of 12.0.0.1 Signed-off-by:
Dick Kennedy <dick.kennedy@broadcom.com> Signed-off-by:
James Smart <james.smart@broadcom.com> Signed-off-by:
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James Smart authored
Update the driver version to 12.0.0.1 Signed-off-by:
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James Smart authored
The driver fails to allocate command buffers in the routine lpfc_new_scsi_buf_s4 There is an inconsistency between lpfc_mem_alloc(), where the phba->lpfc_sg_dma_buf_pool is created, and lpfc_new_scsi_buf_s4(), when we allocate a buffer from the pool and check the alignment. The alignment should be on a page boundary, based on LPFC_SLI3_BG_ENABLED in sli3_options, for both cases. Fix by explicitly tracking sli4 vs sli3 and BG options. The result is that phba->cfg_sg_dma_buf_size is now set correctly for SLI-4. Signed-off-by:
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James Smart authored
POST_SGL_PAGES mailbox command failed with status (timeout). wait_event_interruptible_timeout when called from mailbox wait interface, gets interrupted, and will randomly fail. Behavior seems very specific to 1 particular server type. Fix by changing from wait_event_interruptible_timeout to wait_for_completion_timeout. Signed-off-by:
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James Smart authored
When a port is configured for NVME and SCSI Initiator support and it probes a target supporting both SCSI and NVME, NVME devices are discovered, but SCSI devices are not. The nlp_fc4_type for all NPorts should be cleared on Link Up or just before GID_FTs get issued, as opposed to just during GID_FT cmpl. RSCN activity as well as Link Up can trigger GID_FT. One GID_FT may complete before the next one is issued. Fix by clearng nlp_fc4_type on link up and just before both GID_FTs are issued. During port swapping, copy nlp_fc4_type to the new ndlp Signed-off-by:
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James Smart authored
To reduce latency when initializing WQE content, created templates for the most common wqes. This reduces the number of operations taken to set the content. It's not a lot of speed up, but every bit helps. This patch updates the NVME target path. [mkp: fixed typo] Signed-off-by:
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James Smart authored
To reduce latency when initializing WQE content, create templates for the most common wqes. This reduces the number of operations taken to set the content. It's not a lot of speed up, but every bit helps. This patch updates the NVME initiator path. [mkp: fixed typo] Signed-off-by:
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James Smart authored
The driver is very sloppy about the WQE structure passed between routines. The base struct type is a 64byte wqe. But in many routines they typecast and access 128byte wqes. There were a couple of cases in the past (corrected already) where the typecasts were incorrectly done and the 64byte buffer was accessed as a 128 byte buffer. Clean this up by properly declaring wqe's as 128byte wqe's and removing the typecasts. 64byte wqes are considered a subset of the 128byte wqes. Signed-off-by:
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James Smart authored
First Burst support was not properly indicated in NVMe PRLI. Correct the bit position and the logic to check and set first burst support. Signed-off-by:
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James Smart authored
Commit 6e8e1c14 ("scsi: lpfc: Add WQ Full Logic for NVME Target") fails the static checker. Checker correctly identified a missing unlock on a return path. Add the unlock. Fixes: 6e8e1c14 ("scsi: lpfc: Add WQ Full Logic for NVME Target") Signed-off-by:
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Souptick Joarder authored
Use dma_pool_zalloc() instead of dma_pool_alloc + memset Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Acked-by:
Brian King <brking@linux.vnet.ibm.com> Signed-off-by:
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- 07 Mar, 2018 4 commits
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James Smart authored
Commit 1351e69f ("scsi: lpfc: Add push-to-adapter support to sli4") fails compilation on some 32-bit systems as writeq() is not supported on all architectures. Additionally, it was pointed out that as writeX() does byteswapping if necessary for pci vs the cpu endianness, the code was broken on BE PPC. After discussions with Arnd Bergmann, we've resolved the issue to the following: Instead of writeX(), use __raw_writeX() - which writes to io space while preserving byte order. To use this, the code was changed to use a different buffer that lpfc prepped via sli_pcimem_bcopy() that was set to the bytestream to be written. On platforms with __raw_writeq support, use the routine, otherwise use __raw_writel() [mkp: checkpatch] Fixes: 1351e69f ("scsi: lpfc: Add push-to-adapter support to sli4") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Jianchao Wang authored
In scsi core, __scsi_queue_insert should just put request back on the queue and retry using the same command as before. However, for blk-mq, scsi_mq_requeue_cmd is employed here which will unprepare the request. To align with the semantics of __scsi_queue_insert, use blk_mq_requeue_request with kick_requeue_list == true and put the reference of scsi_device. Cc: Christoph Hellwig <hch@lst.de> Signed-off-by:
Jianchao Wang <jianchao.w.wang@oracle.com> Reviewed-by:
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Souptick Joarder authored
Use dma_pool_zalloc() instead of dma_pool_alloc + memset Signed-off-by:
Sumit Saxena <sumit.saxena@broadcom.com> Signed-off-by:
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Kevin Barnett authored
Reviewed-by:
Scott Benesh <scott.benesh@microsemi.com> Signed-off-by:
Kevin Barnett <kevin.barnett@microsemi.com> Signed-off-by:
Don Brace <don.brace@microsemi.com> Signed-off-by:
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- 06 Mar, 2018 1 commit
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Arnd Bergmann authored
The newly added code mixes up phys_addr_t/resource_size_t with dma_addr_t and void pointers, as seen from these compiler warning: drivers/scsi/mpt3sas/mpt3sas_base.c: In function '_base_get_chain_phys': drivers/scsi/mpt3sas/mpt3sas_base.c:235:21: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] base_chain_phys = (void *)ioc->chip_phys + MPI_FRAME_START_OFFSET + ^ drivers/scsi/mpt3sas/mpt3sas_base.c: In function '_clone_sg_entries': drivers/scsi/mpt3sas/mpt3sas_base.c:427:20: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] sgel->Address = (dma_addr_t)dst_addr_phys; ^ drivers/scsi/mpt3sas/mpt3sas_base.c:438:7: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] (dma_addr_t)buff_ptr_phys; ^ drivers/scsi/mpt3sas/mpt3sas_base.c:444:10: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] (dma_addr_t)buff_ptr_phys; Both dma_addr_t and phys_addr_t may be wider than a pointer, so we must avoid the conversion to pointer types. This also helps readability. A second problem is treating MMIO addresses from a 'struct resource' as addresses that can be used for DMA on that device. In almost all cases, those are the same, but on some of the more obscure architectures, PCI memory address 0 is mapped into the CPU address space at a nonzero offset. I don't have a good fix for that, so I'm adding a comment here, plus a WARN_ON() that triggers whenever the phys_addr_t number is outside of the low 32-bit address space and causes a straight overflow when assigned to the 32-bit sgel->Address. Fixes: 182ac784 ("scsi: mpt3sas: Introduce Base function for cloning.") Signed-off-by:Sreekanth Reddy <Sreekanth.Reddy@broadcom.com> Signed-off-by:
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- 02 Mar, 2018 5 commits
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Weiping Zhang authored
Add a file for documenting SCSI sd module parameters and describe the cache_type setting. [mkp: tweaked text a bit] Signed-off-by:
Weiping Zhang <zhangweiping@didichuxing.com> Signed-off-by:
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Dan Carpenter authored
On 64 bit CPUs there is a memory corruption bug on probe(). It should be a u32 pointer instead of an unsigned long pointer or we write past the end of the setupdata[] array. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Hannes Reinecke <hare@suse.com> Signed-off-by:
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Wilfried Weissmann authored
This patch fixes the byte order of the SGPIO api and brings it back in sync with ledmon v0.80 and above. [mkp: added missing SoB and fixed whitespace] Signed-off-by:
Wilfried Weissmann <wilfried.weissmann@gmx.at> Signed-off-by:
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Bart Van Assche authored
Avoid that the kernel-doc tool complains about mismatches between kernel-doc headers and function definitions. Avoid that errors like the following are reported when building the UFS driver with W=1: drivers/scsi/ufs/tc-dwc-g210-pci.c:60: error: Cannot parse struct or union! drivers/scsi/ufs/tc-dwc-g210-pltfrm.c:26: warning: cannot understand function prototype: 'struct ufs_hba_variant_ops tc_dwc_g210_20bit_pltfm_hba_vops = ' Signed-off-by:
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Bart Van Assche authored
Avoid that the kernel-doc tool complains about a mismatch between the kernel-doc header and the function argument list. Signed-off-by:
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- 28 Feb, 2018 7 commits
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Suganath Prabu S authored
Sending I/O through 32 bit descriptors to Ventura series of controller results in IO timeout on certain conditions. This error only occurs on systems with high I/O activity. Changes in this patch will prevent driver from using 32 bit descriptor and use 64 bit Descriptors Signed-off-by:
Suganath Prabu S <suganath-prabu.subramani@broadcom.com> Reviewed-by:
Tomas Henzl <thenzl@redhat.com> Reviewed-by:
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Suganath Prabu Subramani authored
If the posted request has an error of any type, the IOC writes a Reply message into a host-based system reply message frame. This functions clone it in the BAR0 mapped region. Signed-off-by:
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Suganath Prabu Subramani authored
1) Added function _base_clone_mpi_to_sys_mem to clone MPI request into system BAR0 mapped region. 2) Separate out MPI Endpoint IO submissions to function _base_put_smid_mpi_ep_scsi_io. 3) MPI EP requests are submitted in two 32 bit MMIO writes. from _base_mpi_ep_writeq. For 32 bit Arch,_base_writeq function is identical to _base_mpi_ep_writeq, Removed duplicate code as suggested. Signed-off-by:
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Suganath Prabu Subramani authored
All scsi IO's and config request's data buffer and sgl are cloned to system memory in _clone_sg_entries before submitting it to firmware. Signed-off-by:
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Suganath Prabu Subramani authored
For MPI Endpoint/Mcpu, driver should double buffer data buffer/SGLs. This is normally copied from host to internal memory of IOC by DMA engine of PCI device. Since the interface to DMA from host to mCPU is not present for Mcpu/MPI Endpoint device, driver does double copy of those buffers directly to the mCPU memory region via BAR0 region. Introduced API to calculate and return BAR0 mapped host buffer's physical and virtual address for the provided smid. Signed-off-by:
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Suganath Prabu Subramani authored
This configures shost max sector to 128, single reply descriptor post queue, sgl table size to 16 and 32 bit DMA for MPI Endpoint and it supports 64K as max IO. Signed-off-by:
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Suganath Prabu Subramani authored
Add device ID and flag for Andromeda/MPI Endpoint. [mkp: typo] Signed-off-by:
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