- 01 Jul, 2020 40 commits
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Tom St Denis authored
Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alvin Lee authored
Get the values from VBIOS table Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Bernard Zhao authored
In function fill_iram_v_2, the ram_table->bright_neg_gain`s first element [0][0] seems to be missing. This change is just to make the code a bit readable. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Joseph Greathouse authored
SDMA ULV can benefit low-power modes, but can sometimes cause latency increases in small SDMA transfers. Server SKUs have a different trade-off space in this domain, so this configures the server SKUs' ULV hysteresis times differently than consumer SKUs'. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lorenz Brun authored
The existing code used the major version number of the DRM driver instead of the device major number of the DRM subsystem for validating access for a devices cgroup. This meant that accesses allowed by the devices cgroup weren't permitted and certain accesses denied by the devices cgroup were permitted (if they matched the wrong major device number). Signed-off-by:
Lorenz Brun <lorenz@brun.one> Fixes: 6b855f7b ("drm/amdkfd: Check against device cgroup") Reviewed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Anthony Koo authored
[Header Changes] - Add new initialization bits for driver to check firmware status - Add command for HW locking via DMUB Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] dmub FW running abnormal after resume from S0i3 due to data aliagnment issue. [How] Before having a solution for this issue, temparory not doing data pack. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] during S0i3, set power state is toggled a few times, and dmub uC will restart with current reset/hw_init. [How] Remove reset in set power state, and before doing hw_init, check if dmub is enabled, and doing FW autoload check only if dmub is already enabled. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dale Zhao authored
[Why] For some special timing with border, like DMT 640*480 72Hz, pipe split can't handle well. Thus, it will be black screen for these special timing. [How] Disable pipe split for these timing with borders as W/A. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] Multi-adapter calculate regamma table at the same time. Two thread used the same global variable cause race condition. [How] Change global buffer to local buffer Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] DC is very fast at link training and stream enablement which causes issues such as blackscreens for non-compliant monitors. [How] After debugging with scaler vendors we implement the minimum delays at the necessary locations to ensure the monitor does not hang. Delays are generic due to lack of IEEE OUI information on the failing displays. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why & How] DMUB command table should be allowed to be used only if dmcu is explicitly disabled. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Dmytro Laktyushkin authored
To allow code reuse with minimal duplication watermark calculation needs to be function pointer. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Rodrigo Siqueira authored
During the debugging process related to a hot-plug problem with 4k display, we realized that we had some issues related to the global state validation. This problem was not explicitly highlighted in the dmesg log, for this reason, this commit adds a function that converts `enum dc_status` to a human-readable string and appends the proper warning message in case of failure. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Jun Lei authored
[why] Dummy pstate latency actually varies between different UCLK frequencies, when calculating watermark C, if DAL always assumes worst case, then it can lead to dummy pstate not supported scenarios. [how] Rather than statically calculating dummy pstate using worst case, we store the entire table of UCLK to dummy pstate relationships. On a per mode basis, we calculate the actual UCLK lower limit, and use the dynamic worst case dummy pstate latency. This prevents the situation where we don't support full p-state (which will force high DPM), but still use low DPM dummy pstate latency. Signed-off-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Wenjing Liu authored
[why] The change causes some regression in a common use case. Will need more investigation before fixing the original issue. [how] This reverts commit fb8cf277. Signed-off-by:
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Dmytro Laktyushkin authored
We were updating mpcc if there were tree changes which is unnecessary since any mpcc being added or removed will automatically update the tree. Signed-off-by:
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Yongqiang Sun authored
[Why & How] Add emul specific hw function to dmub, in case of emulator is created, we can runtime switch between dmub emulator or dmub uC via is_virtual flag in dmub. Signed-off-by:
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po-tchen authored
[Why] The SDP deadline indicate the vertical time to send CRC infopacket in PSR. Signed-off-by:
po-tchen <po-ting.chen@amd.com> Reviewed-by:
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Martin Tsai authored
[Why] Some sprcified monitor scalar cannot recognize timing change on demand. Once the link phy disable and enable during a short period then the Sink protection mechanism could keep the screen in blank and cannot be recoverred. [How] To add 100ms delay between enable link phy and link training. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Anthony Koo authored
[Header Changes] - Add SDP transmission deadline for PSR config cmd Signed-off-by: -
Charlene Liu authored
[why] for audio on real TV issue. [how] -add wall clock programming for DPREF based when Pixel clock is done by DP DTO. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DML failures occur for 420 modes with dynamic pipe splitting enabled because the ChromaViewport exceeds the ChromaSurfaceWidth. This is caused by adding the viewport_width instead of the viewport_width_c. This similarly occurs for rotated modes due to the use of viewport_height instead of viewport_height_c. [How] Correct the calculations. Signed-off-by:
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Hugo Hu authored
This reverts commmit fd0293dd. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Roman Li authored
[Why] SOC_BOUNDING_BOX_VALID is unused and not required for dcn21. [How] Remove it. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] DSC calculations fail because the u16 bits_per_pixel from the DRM struct is being casted to the u8 drm_bpp parameters and locals. Integer wraparound is happening because this value is greater than 255. [How] Use u16 to match what's in the structure instead of u8. Signed-off-by:
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Wesley Chalmers authored
[WHY] Disabling DPG should happen after setting watermarks and clocks Signed-off-by:
Wesley Chalmers <wchalmer@amd.com> Reviewed-by:
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Anthony Koo authored
[Header Changes] - Version bump to 1.0.13 Signed-off-by: -
Michael Strauss authored
[WHY] Typos cause bandwidth calculation errors, one of which can cause infinite loop on dcn1 with eDP Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
When we want to use float point operation on Linux we need to use within special kernel protection (`kernel_fpu_{begin,end}()`.), otherwise the kernel can clobber userspace FPU register state. For detecting these issues we use a tool named objtool (with -Ffa flags) to highlight the FPU problems, all warnings can be summed up as follows: ./tools/objtool/objtool check -Ffa drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.o [..] dc/dsc/rc_calc.o: warning: objtool: get_qp_set()+0x2f8: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: dsc_roundf()+0x5: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: dsc_ceil()+0x5: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: get_ofs_set()+0x3eb: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: calc_rc_params()+0x3c: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/dc_dsc.o: warning: objtool: get_dsc_bandwidth_range.isra.0()+0x8d: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/dc_dsc.o: warning: objtool: setup_dsc_config()+0x2ef: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc_dpi.o: warning: objtool:copy_pps_fields()+0xbb: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc_dpi.o: warning: objtool: dscc_compute_dsc_parameters()+0x7b: FPU instruction outside of kernel_fpu_{begin,end}() This commit fixes the above issues by rework DSC as described: 1. Isolate all FPU operations in a single file; 2. Use FPU flags only in the file that handles FPU operations; 3. Isolate all functions that require float point operation in static functions; 4. Add a mid-layer function that does not use any float point operation, and that could be safely invoked in other parts of the code. 5. Keep float point operation under DC_FP_{START/END} macro. CC: Christian König <christian.koenig@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Peter Zijlstra <peterz@infradead.org> CC: Tony Cheng <tony.cheng@amd.com> CC: Harry Wentland <hwentlan@amd.com> Signed-off-by:Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Charlene Liu authored
[why] for following new format, no alpha SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT/_FIX: SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT/_FIX same as case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: Signed-off-by: -
Tom St Denis authored
Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by:
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James Zhu authored
Fix race condition issue when multiple jpeg starts are called. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Emily Deng authored
As will clear vf fw during unload driver, to avoid idle fail. Need to clear KIQ portion also. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Ack-by:
Monk.liu <monk.liu@amd.com> Signed-off-by:
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Emily Deng authored
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Emily Deng authored
Guest VM issue the PSP clear_vf_fw command at 2 points: 1.On VF driver loading, after VF message PSP to setup rings, the next command is “clear_vf_fw” 2.On VF driver unload before VF message to destroy rings Signed-off-by:
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Prike.Liang authored
Fixes: c1cf79ca ("drm/amdgpu: use IP discovery table for renoir") This nullptr issue should be specific on the Renoir series during try access the PWR_MISC_CNTL_STATUS when PWR IP not been detected by discovery table. Moreover the PWR IP not existing in Renoir series is expected therefore just avoid access PWR register in Renoir series. Signed-off-by:
Prike.Liang <Prike.Liang@amd.com> Acked-by:
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Sandeep Raghuraman authored
Initializes Powertune data for a specific Hawaii card by fixing what looks like a typo in the code. The device ID 66B1 is not a supported device ID for this driver, and is not mentioned elsewhere. 67B1 is a valid device ID, and is a Hawaii Pro GPU. I have tested on my R9 390 which has device ID 67B1, and it works fine without problems. Signed-off-by:
Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by:
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