- 06 Dec, 2016 1 commit
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Stephen Boyd authored
Merge tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP), a fix making sure the cpuclk rate is actually valid, before trying to set it and a copy-paste fix for the rk3399's testclk. * tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock controller for rk1108 dt-bindings: add documentation for rk1108 cru clk: rockchip: add dt-binding header for rk1108 clk: rockchip: fix copy-paste error in rk3399 testclk clk: rockchip: validity should be checked prior to cpu clock rate change
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- 24 Nov, 2016 2 commits
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Sricharan R authored
The venus video ip's internal core blocks are under the control of the firmware and their powerdomains needs to be 'ON' only when used by the firmware. So putting it into hw controlled mode lets this to happen, otherwise the firmware hangs checking for this. Signed-off-by:
Sricharan R <sricharan@codeaurora.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Rajendra Nayak authored
Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
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- 23 Nov, 2016 8 commits
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Stephen Boyd authored
* clk-fixes: clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
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Florian Fainelli authored
With commit f4e87150 ("clk: iproc: Make clocks visible options"), COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX also selects that option, this causes the following Kconfig warning: warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK) Fix this by adding proper depends for COMMON_CLK_IPROC Fixes: f4e87150 ("clk: iproc: Make clocks visible options") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Ray Jui <ray.jui@broadcom.com> [sboyd@codeaurora.org: Drop default part as it's redundant] Signed-off-by:
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Icenowy Zheng authored
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control register is called "LDO{1,2}_EN", and according to the BSP source code from Allwinner [1], the LDOs are enabled during the clock's enabling process. The clock failed to generate output if the two LDOs are not enabled. Add the two bits to the clock's gate bits, so that the LDOs are enabled when the PLL is enabled. [1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429 Fixes: d05c748b ("clk: sunxi-ng: Add A33 CCU support") Signed-off-by:Icenowy Zheng <icenowy@aosc.xyz> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Boris Brezillon authored
There is no fixed divider on pllh_aux. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
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Georgi Djakov authored
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by:
Michael Scott <michael.scott@linaro.org> Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Georgi Djakov authored
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by:
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Rajendra Nayak authored
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084 expects a clk_set_rate() on the sdcc rcg clk to set a floor value of supported clk rate closest to the requested rate, by looking up the frequency table. So move all the sdcc rcgs on all these platforms to use the newly introduced clk_rcg2_floor_ops Signed-off-by:
Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by:
Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by:
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Rajendra Nayak authored
The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by:
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- 22 Nov, 2016 1 commit
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git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull Exynos5433 SoC updates from Sylwester Nawrocki: - addition of missing documentation and DT properties for the CMU_AUD block source clocks, - correction of CMU_FSYS parent clock definition, - marking as critical clocks which have to be enabled in order to access control registers of child CMUs. * tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung: clk: exynos5433: Mark some clocks as critical clk: exynos5433: Add documentation for the audio block parent clocks clk: exynos5433: Fix parent clocks for FSYS block
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- 21 Nov, 2016 1 commit
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Chen-Yu Tsai authored
The PLL-MIPI clock is somewhat special as it has its own LDOs which need to be turned on for this PLL to actually work and output a clock signal. Add the 2 LDO enable bits to the gate bits. This fixes issues with the TCON not sending vblank interrupts when the tcon and dot clock are indirectly clocked from the PLL-MIPI clock. Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by:
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- 18 Nov, 2016 1 commit
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Marek Szyprowski authored
Some parent clocks of the Exynos5433 CMUs must be always enabled to access any register in the given CMU or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused) to prevent disabling them. Reported-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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- 17 Nov, 2016 4 commits
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull more clk driver updates from Geert Uytterhoeven: - CSI2 and VIN clocks for R-Car M3-W, - Clock drivers for new RZ/G1M and RZ/G1E SoCs, - Minor bug fix for R-Car H3. * tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add R8A7745 support clk: renesas: cpg-mssr: Add R8A7743 support clk: renesas: cpg-mssr: Add common R-Car Gen2 support clk: renesas: r8a7795: Fix HDMI parent clock clk: renesas: r8a7796: Add VIN clocks clk: renesas: r8a7796: Add CSI2 clocks
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geerty Uytterhoeven: - Add R-Car RST driver for obtaining mode pin state, and move the related functionality from platform code to DT, - Add r8a7743 and r8a7745 CPG Core Clock Definitions. The commits here are intermingled with arm-soc material because of the hard dependency we're breaking between mach code and driver code. We're replacing that with a driver dependency between the soc driver and the clk driver. * tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (25 commits) clk: renesas: Add r8a7745 CPG Core Clock Definitions clk: renesas: Add r8a7743 CPG Core Clock Definitions clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init() clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init() clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init() ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver ARM: shmobile: r8a7779: Stop passing mode pins state to clock driver ARM: shmobile: r8a7778: Stop passing mode pins state to clock driver clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins() clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver clk: renesas: rcar-gen2: Obtain mode pin values using RST driver clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driver clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driver arm64: renesas: r8a7796 dtsi: Add device node for RST module arm64: renesas: r8a7795 dtsi: Add device node for RST module ARM: dts: r8a7794: Add device node for RST module ARM: dts: r8a7793: Add device node for RST module ARM: dts: r8a7792: Add device node for RST module ARM: dts: r8a7791: Add device node for RST module ...
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Marek Szyprowski authored
Audio block requires access to two parent clocks: audio PLL and oscillator, so add this information to device tree bindings documentation. Signed-off-by:
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Marek Szyprowski authored
The proper parent clock for FSYS block is "aclk_fsys_200" according to the Exynos5433 reference manual. Signed-off-by:
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- 16 Nov, 2016 12 commits
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Stephen Boyd authored
Some checkpatch warnings about spaces were missed and we didn't mark two structs as static. Clean it up. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: -
Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock changes from Maxime Ripard: The usual patches from us, but most notably the introduction of the A64 clocks unit. * tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks clk: sunxi-ng: Add A64 clocks clk: sunxi-ng: Implement minimum for multipliers clk: sunxi-ng: Add minimums for all the relevant structures and clocks clk: sunxi-ng: Finish to convert to structures for arguments clk: sunxi-ng: Remove the use of rational computations clk: sunxi-ng: Rename the internal structures clk: sunxi: mod0: improve function-level documentation
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Stephen Boyd authored
Merge tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clock updates from Shawn Guo: - A patch series to fix the long standing issue with glitchy parent mux of ldb_di_clk, which can hang up LVDS display when ipu_di_clk is sourced from ldb_di_clk. - A patch to add imx6ull clock support on top of imx6ul clock driver. * tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: clk-imx6ul: add clk support for imx6ull clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf
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Stephen Boyd authored
* clk-fixes: clk: efm32gg: Pass correct type to hw provider registration clk: berlin: Pass correct type to hw provider registration clk: sunxi: Fix M factor computation for APB1 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
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Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Pull Allwinner clock fixes from Maxime Ripard: Two fixes, one for the old clock code, one for the new implementation. * tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Fix M factor computation for APB1 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
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Stephen Boyd authored
Dan Carpenter reports that we're passing a pointer to a pointer here when we should just be passing a pointer. Pass the right pointer so that the of_clk_hw_onecell_get() sees the appropriate data pointer on its end. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Fixes: 9337631f ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs") Signed-off-by:
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Stephen Boyd authored
Dan Carpenter reports that we're passing a pointer to a pointer here when we should just be passing a pointer. Pass the right pointer so that the of_clk_hw_onecell_get() sees the appropriate data pointer on its end. Reported-by:
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Shawn Lin authored
Add the clock tree definition and driver for rk1108 SoC. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Tested-by:
Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
This adds the dt-binding documentation for the clock and reset unit found on Rockchip rk1108 SoCs. Signed-off-by:
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Heiko Stuebner authored
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Shawn Lin authored
Add the dt-bindings header for the rk1108, that gets shared between the clock controller and the clock references in the dts. Signed-off-by:
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Jianqun Xu authored
Fix RK3368_* to RK3399_* for rk3399 clk_test clock. Signed-off-by:
Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by:
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- 15 Nov, 2016 4 commits
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Leo Yan authored
In current kernel config 'CONFIG_STUB_CLK_HI6220' is disabled by default, as result stub clock driver has not been registered and CPUFreq driver cannot work. This patch is to enable stub clock driver in config for ARCH_HISI. Reported-by:
Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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Stephen Boyd authored
Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: PLL initialization for PLLs having both an integral and fractional mode (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. * tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree clk: rockchip: add 400MHz to rk3066 clock rates table clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 clk: rockchip: add 533.25MHz to rk3399 clock rates table
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - SYS-DMAC, (H)SCIF, I2C, DRIF, and graphics related clocks for R-Car M3-W, - Minor fixes and cleanups. * tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add DU and LVDS clocks clk: renesas: r8a7796: Add VSP clocks clk: renesas: r8a7796: Add FCP clocks clk: renesas: cpg-mssr: Remove bogus commas from error messages clk: renesas: r8a7796: Add DRIF clock clk: renesas: cpg-mssr: Fix inverted debug check clk: renesas: rcar-gen3-cpg: Always use readl()/writel() clk: renesas: cpg-mssr: Always use readl()/writel() clk: renesas: r8a7796: Add I2C clocks clk: renesas: r8a7796: Add HSCIF clocks clk: renesas: r8a7796: Add SCIF clocks clk: renesas: r8a7796: Add SYS-DMAC clocks
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Bai Ping authored
imx6ull is the derived SoC from imx6ul Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Bai Ping <ping.bai@nxp.com> Signed-off-by:
Peter Chen <peter.chen@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- 14 Nov, 2016 3 commits
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Stephen Boyd authored
* clk-hisi: clk: hisilicon: add CRG driver for Hi3516CV300 SoC clk: hisilicon: add CRG driver for Hi3798CV200 SoC
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Pan Wen authored
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by:
Pan Wen <wenpan@hisilicon.com> Signed-off-by:
Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by:
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Elaine Zhang authored
If validity is not checked prior to clock rate change, clk_set_rate( cpu_clk, unsupported_rate) will return success, but the real clock rate change operation is prohibited in post clock change event. Alough post clock change event will report error due to unsupported clock rate is set, but this error message is ignored by clock framework. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Tested-by:
Rocky Hao <rocky.hao@rock-chips.com> Signed-off-by:
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- 11 Nov, 2016 3 commits
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Jiancheng Xue authored
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Chen-Yu Tsai authored
The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks") Signed-off-by:
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Chen-Yu Tsai authored
The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes: 5690879d ("clk: sunxi-ng: Add A23 CCU") Signed-off-by:
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