- 24 Apr, 2017 16 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.12-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 (take three) - Miscellaneous fixes for R-Car M2-W and R-Car E2.
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Colin Ian King authored
trivial fix to spelling mistake in documentation Signed-off-by:
Colin Ian King <colin.king@canonical.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Paul Gortmaker authored
The Kconfig currently controlling compilation of this code is: drivers/pinctrl/Kconfig:config PINCTRL_ARTPEC6 drivers/pinctrl/Kconfig: bool "Axis ARTPEC-6 pin controller driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Lars Persson <lars.persson@axis.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: linux-arm-kernel@axis.com Cc: linux-gpio@vger.kernel.org Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by:
Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
Several pinconf parameters have a fairly straight-forward mapping onto the Aspeed pin controller. These include management of pull-down bias, drive-strength, and some debounce configuration. Pin biasing largely is managed on a per-GPIO-bank basis, aside from the ADC and RMII/RGMII pins. As the bias configuration for each pin in a bank maps onto a single per-bank bit, configuration tables will be introduced to describe the ranges of pins and the supported pinconf parameter. The use of tables also helps with the sparse support of pinconf properties, and the fact that not all GPIO banks support biasing or drive-strength configuration. Further, as the pin controller uses a consistent approach for bias and drive strength configuration at the register level, a second table is defined for looking up the the bit-state required to enable or query the provided configuration. Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU. The test method was to set the appropriate bits via devmem and verify the result through the controller's pinconf-pins debugfs file. This simultaneously validates the get() path and half of the set() path. The remainder of the set() path was validated by configuring a handful of pins via the devicetree with the supported pinconf properties and verifying the appropriate registers were touched. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Alexandre TORGUE authored
Add new compatible for stm32f469 MCU. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Alexandre TORGUE authored
This patch which adds STM32F469 pinctrl and GPIO support, relies on the generic STM32 pinctrl driver. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Alexandre TORGUE authored
Remove "ngpios" bindings definition as it is no more used in stm32 pinctrl driver. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Alexandre TORGUE authored
Pinctrl has to be registered earlier. Mainly to register bank irqdomain earlier as other devices could use interrupts from those irqdomain. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Alexandre TORGUE authored
Use device tree entries to declare gpio range. It will allow to use no contiguous gpio bank and holes inside a bank. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Gregory CLEMENT authored
GPIO management is pretty simple and is part of the same IP than the pin controller for the Armada 37xx SoCs. This patch adds the GPIO support to the pinctrl-armada-37xx.c file, it also allows sharing common functions between the gpiolib and the pinctrl drivers. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Gregory CLEMENT authored
The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Gregory CLEMENT authored
Document the device tree binding for the pin controllers found on the Armada 37xx SoCs. Update the binding documention of the xtal clk which is a subnode of this syscon node. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Rob Herring <robh@kernel.org> [Fixed gpios node] Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Andy Shevchenko authored
pinctrl_init_controller() is not used outside core.c, thus make it static and prevent compiler to warn. drivers/pinctrl/core.c:1943:21: warning: no previous prototype for ‘pinctrl_init_controller’ [-Wmissing-prototypes] struct pinctrl_dev *pinctrl_init_controller(struct pinctrl_desc *pctldesc, ^~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 11 Apr, 2017 2 commits
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Jacopo Mondi authored
Add bi-directional and output-enable pin configuration properties. bi-directional allows to specify when a pin shall operate in input and output mode at the same time. This is particularly useful in platforms where input and output buffers have to be manually enabled. output-enable is just syntactic sugar to specify that a pin shall operate in output mode, ignoring the provided argument. This pairs with input-enable pin configuration option. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
Three video input signals suffered from a search/replace failure in some copied code. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 10 Apr, 2017 1 commit
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Linus Walleij authored
Merge tag 'samsung-pinctrl-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers update for v4.12: 1. Add support for pad retention control through pinctrl drivers which moves us forward to better runtime PM of pinctrl, clocks, power domains and other devices. 2. Fix GPIO hogs by registering pinctrl before registering gpiolib. 3. Use devm-like interface.
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- 07 Apr, 2017 7 commits
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Alexandre Belloni authored
When suspending to RAM, the power to the core is cut and the register values are lost. Save and restore more registers than just IMR. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jacopo Mondi authored
Document "pinmux" property as part of generic pin controller documentation. Fix 2 minor typos in documentation while at there. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
Correct the incorrect function name and description. Fixes: a76edc89 ("pinctrl: core: Add generic pinctrl functions for managing groups") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jesper Nilsson authored
Add pinctrl driver support for the Axis ARTPEC-6 SoC. There are only some pins that actually have different functions available, but all can control bias (pull-up/-down) and drive strength. Code originally written by Chris Paterson. Signed-off-by:
Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jesper Nilsson authored
Add the bindings for the pinmux functions in the ARTPEC-6 SoC, including bias and drive strength. Signed-off-by:
Jesper Nilsson <jesper.nilsson@axis.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1. However, they both seem to have the same function, just exposed on different pins (unlike the ethernet TX pins for example, where there's eth_txd0..3 - all of these can be active at the same time as they are different data lines). Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that it's the same functionality just exposed on different pins (BOOT_15 and BOOT_18). Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Martin Blumenstingl authored
The nand_groups table uses different names for the NAND DQS pins than the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). This prevents using the NAND DQS pins in the devicetree. Fix this by ensuring that the GROUP() definition and the meson8b_cbus_groups use the same name for these pins. Fixes: 0fefcb68 ("pinctrl: Add support for Meson8b") Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 05 Apr, 2017 1 commit
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Sergei Shtylyov authored
All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this. Fixes: 43c4436e ("pinctrl: sh-pfc: add R8A7794 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 04 Apr, 2017 5 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.12 (take two) - Add basic support for the Pin Function Controller on revision ES2.0 of the R-Car H3 SoC, which differs from ES1.x in many ways.
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Sergei Shtylyov authored
The IPSR field names in the comments have been fat-fingered in a couple places -- fix those silly typos... Fixes: 50884519 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Sergei Shtylyov authored
PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong 1st argument -- most probably a result of cut&paste programming... Fixes: 50884519 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Sergei Shtylyov authored
The R8A7791 PFC driver was apparently based on the preliminary revisions of the user's manual, which omitted the DVC_MUTE signal altogether in the PFC section. The modern manual has the signal described, so just add the necassary data to the driver... Fixes: 50884519 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Sergei Shtylyov authored
The R8A7791 PFC driver was apparently based on the preliminary revisions of the user's manual, which omitted the HSCIF1 group E signals in the IPSR4 register description. This would cause HSCIF1's probe to fail with the messages like below: sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989 sh-sci e62c8000.serial: Error applying setting, reverse things back sh-sci: probe of e62c8000.serial failed with error -22 Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E, HCTS1#_E, and HRTS1#_E signals... Fixes: 50884519 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 30 Mar, 2017 3 commits
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Geert Uytterhoeven authored
Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0. SCIF_CLK is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF serial ports. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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Geert Uytterhoeven authored
Add pins, groups, and functions for all SCIF serial ports on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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Geert Uytterhoeven authored
The Pin Function Controller module in the R-Car H3 ES2.0 differs from ES1.x in many ways. The goal is twofold: 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary for now, 2. Make it clear which code supports ES1.x, so it can easily be identified and removed later, when production SoCs are deemed ubiquitous. Hence this patch: 1. Extracts the support for R-Car H3 ES1.x into a separate file, as the differences are quite large, 2. Adds code for detecting the SoC revision at runtime using the new soc_device_match() API, and selecting pinctrl tables for the actual SoC revision, 3. Replaces the core register and bitfield definitions by their counterparts for R-Car H3 ES2.0. The addition of pins, groups, and functions for the various on-chip devices is left to subsequent patches. The R-Car H3 ES2.0 register and bitfield definitions were extracted from a patch in the BSP by Takeshi Kihara. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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- 28 Mar, 2017 5 commits
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Jerome Brunet authored
Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jerome Brunet authored
Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jerome Brunet authored
Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jerome Brunet authored
Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Neil Armstrong authored
When trying to add a gpio-hog, we enter a weird loop where the gpio-ranges is needed when gpiochip_add_data() is called but in the current implementation the ranges are added from the driver afterwards. A simple solution is to rely on the DR gpio-ranges attribute and remove the call to gpiochip_add_pin_range(). Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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