- 26 Jun, 2023 1 commit
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Bjorn Andersson authored
Merge the missing SC8280XP LPASS DeviceTree changes, which where brought in through a topic branch in order to be shared with the DeviceTree source files, but not merged into the clock tree until now.
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- 20 Jun, 2023 3 commits
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Konrad Dybcio authored
The GCC block on SC8280XP is powered by the CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230619-topic-sc8280xp-clk-rpm-v1-2-1e5e1064cdb2@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
The GPU_CC block on SC8280XP is powered by the GFX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by:
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Dmitry Baryshkov authored
Using PWRSTS_RET on msm8974's MDSS_GDSC causes display to stop working. The gdsc doesn't fully come out of retention mode. Change it's pwrsts flags to PWRSTS_OFF_ON. Fixes: d3997239 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Tested-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20230507175335.2321503-2-dmitry.baryshkov@linaro.orgSigned-off-by:
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- 13 Jun, 2023 13 commits
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Konrad Dybcio authored
The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter rail is not online, GX_GDSC will never turn on. Enable runtime pm so that we can reference VDD_GX from the dt to ensure that. Signed-off-by:
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Konrad Dybcio authored
The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter rail is not online, GX_GDSC will never turn on. Describe the missing handles. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Konrad Dybcio authored
When the driver was ported upstream, PLL ctl register values were omitted. Add them to ensure the PLLs are fully configured like we expect them to. Fixes: cbe63bfd ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by:
Iskren Chernev <me@iskren.info> Signed-off-by:
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Konrad Dybcio authored
The "vanilla" Alpha PLL configs are sometimes provided with an intention to only update certain bits of th register. Do so if a mask is found. Signed-off-by:
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Arnd Bergmann authored
A recent change added new initializers for .config_ctl_val and .config_ctl_hi_val but left the old values in place: drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init] 4155 | .config_ctl_val = 0x240d4828, | ^~~~~~~~~~ drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init] 4156 | .config_ctl_hi_val = 0x6, | ^~~ Remove the unused ones now to avoid confusion. Fixes: f4f0c8ac ("clk: qcom: gcc-ipq6018: update UBI32 PLL") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Anusha Rao authored
Enable the clocks required for crypto operation. Reviewed-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the DeviceTree binding updates for IPQ9574 GCC adding clocks and resets related to Crypto Engine, through a topic branch in order to make them available in the DeviceTree source tree as well.
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Anusha Rao authored
Add crypto clock and reset ID definitions for ipq9574. Acked-by:
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Srinivas Kandagatla authored
Add support for the lpass audio clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Srinivas Kandagatla authored
Add support for the lpass clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by:
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Srinivas Kandagatla authored
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by:
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Srinivas Kandagatla authored
The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by:
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Luca Weiss authored
Define clock/clock-names properties of the MMCC device node to be used on MSM8226 platform. Signed-off-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by:
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- 27 May, 2023 7 commits
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Jagadeesh Kona authored
Add support for gpucc driver on SM8550, which provides clocks for the graphics subsystem. Co-developed-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
The GPUCC manages the clocks for the Adreno GPU found on the sm8450 SoCs. Signed-off-by:
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Konrad Dybcio authored
Enable hardware clock control on all RCGs. Signed-off-by:
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Konrad Dybcio authored
Certain SoCs use the HW_CLK_CTRL feature on some of the clocks they host. This allows the clocks to be turned on automatically when a downstream branch tries to change rate or config. Make it togglable so that we can utilize this. Signed-off-by:
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Bjorn Andersson authored
Bring GPUCC DeviceTree bindings for SM8450 and SM8550 in through a topic branch to allow sharing it with the DeviceTree source tree as well.
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Jagadeesh Kona authored
Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by:
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- 26 May, 2023 9 commits
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Dmitry Baryshkov authored
The mdp_clk_src clock should not be turned off. Instead it should be 'parked' to the XO, as most of other mdp_clk_src clocks. Fix that by using the clk_rcg2_shared_ops. Fixes: d8b21201 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by:
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Kathiravan T authored
The order of DT_SLEEP_CLK and DT_XO are swapped and it is incorrect. Due to which the clocks for which the parent should be XO is having parent as SLEEP_CLK and vice versa. So fix the same by re-ordering the entries. Fixes: 3d89d529 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by:
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Kathiravan T authored
480MHz is derived from P_GPLL4_OUT_AUX not from P_GPLL4_OUT_MAIN. Update the freq_tbl with the correct src. Fixes: 3d89d529 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by:
Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by:
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Konrad Dybcio authored
GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously made to reuse the same parent enum entry as GPLL0_OUT_MAIN (.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3 ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by:
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Konrad Dybcio authored
BI_TCXO_AO (.fw_name = "bi_tcxo_ao") was previously made to reuse the same parent enum entry as BI_TCXO (.fw_name = "bi_tcxo") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3 ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by:
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Robert Marko authored
Networking resets in IPQ6018 all use bitmask as they require multiple bits to be set and cleared instead of a single bit. So, current networking resets have the same register and bit 0 set which is clearly incorrect. Fixes: d9db07f0 ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by:
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Robert Marko authored
Update the UBI32 alpha PLL config to the latest values from the downstream QCA 5.4 kernel. Signed-off-by:
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Devi Priya authored
Add the compatible and configuration values for A73 Huayra PLL found on IPQ9574. Co-developed-by:
Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Reviewed-by:
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Devi Priya authored
IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53 bindings as the PLL properties match with that of A53. Acked-by:
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- 25 May, 2023 7 commits
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Krzysztof Kozlowski authored
The GCC clock controller needs CX power domain, at least according to DTS: sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by:Rob Herring <robh@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
The GCC clock controller needs CX power domain, at least according to DTS: sc7180-trogdor-pompom-r3.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by: -
Krzysztof Kozlowski authored
The initial SM8250 GCC driver added in commit 3e577092 ("clk: qcom: gcc: Add global clock controller driver for SM8250") already consumed it on the clock. This fixes warnings like: sm8250-xiaomi-elish-csot.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too long Fixes: 98394efb ("dt-bindings: clock: Add SM8250 GCC clock bindings") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
There is no point to allow selecting clock controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs model names/numbers. No features should be lost because: 1. There won't be a single image for ARMv7 and ARMv8/9 SoCs. 2. Newer ARMv8/9 SoCs won't be running in arm32 emulation mode. Signed-off-by:
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Imran Shaik authored
Add Global Clock Controller (GCC) support for SDX75 platform. Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by:
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Imran Shaik authored
Add support for RPMH clocks for SDX75 platform. Signed-off-by:
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Imran Shaik authored
Add compatible string for qcom RPMHCC for SDX75 platform. Signed-off-by:
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