- 26 Feb, 2024 1 commit
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Théo Lebrun authored
Current behavior is that spi-mem operations do not increment statistics, neither per-controller nor per-device, if ->exec_op() is used. For operations that do NOT use ->exec_op(), stats are increased as the usual spi_sync() is called. The newly implemented spi_mem_add_op_stats() function is strongly inspired by spi_statistics_add_transfer_stats(); locking logic and l2len computation comes from there. Statistics that are being filled: bytes{,_rx,_tx}, messages, transfers, errors, timedout, transfer_bytes_histo_*. Note about messages & transfers counters: in the fallback to spi_sync() case, there are from 1 to 4 transfers per message. We only register one big transfer in the ->exec_op() case as that is closer to reality. This patch is NOT touching: - spi_async, spi_sync, spi_sync_immediate: those counters describe precise function calls, incrementing them would be lying. I believe comparing the messages counter to spi_async+spi_sync is a good way to detect ->exec_op() calls, but I might be missing edge cases knowledge. - transfers_split_maxsize: splitting cannot happen if ->exec_op() is provided. Reviewed-by:Dhruva Gole <d-gole@ti.com> Signed-off-by:
Théo Lebrun <theo.lebrun@bootlin.com> Reviewed-by:
Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://msgid.link/r/20240216-spi-mem-stats-v2-1-9256dfe4887d@bootlin.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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- 21 Feb, 2024 3 commits
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Théo Lebrun authored
Set the ->num_chipselect field in struct cqspi_st and struct spi_controller to the current number of chip-select. The value is dependent on declared flashes in devicetree. Previously, the num-cs property from devicetree or the maximum value was being reported. Signed-off-by:
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Théo Lebrun authored
Change the maximum chip-select count in cadence-qspi to 4 instead of 16. The value gets used as default ->num_chipselect when the num-cs DT property isn't received from devicetree. It also determines the cqspi->f_pdata array size. Hardware only supports values up to 4; see cqspi_chipselect() that sets CS using a one-bit-per-CS 4-bit register field. Add a static_assert() call as a defensive measure to ensure we stay under the SPI subsystem limit. It got set to 4 when introduced in 4d8ff6b0 ("spi: Add multi-cs memories support in SPI core") and later increased to 16 in 2f8c7c37 ("spi: Raise limit on number of chip selects"). Signed-off-by:
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Théo Lebrun authored
Check each flash CS against the num-cs property from devicetree. Fallback to the driver max supported value (CQSPI_MAX_CHIPSELECT) if num-cs isn't present. cqspi->num_chipselect is set in cqspi_of_get_pdata() to the num-cs devicetree property, or to CQSPI_MAX_CHIPSELECT if num-cs is not set. Signed-off-by:
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- 19 Feb, 2024 1 commit
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Randy Dunlap authored
The change to use "target" requires an underline to be extended by one more character to fix a documentation build warning: Documentation/spi/spi-summary.rst:274: WARNING: Title underline too short. Declare target Devices ^^^^^^^^^^^^^^^^^^^^^ Fixes: hash ("spi: Update the "master/slave" terminology in documentation") Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Cc: Dhruva Gole <d-gole@ti.com> Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Reviewed-by:
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- 15 Feb, 2024 2 commits
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Dhruva Gole authored
Update the master/slave terminology wherever possible to adopt usage of the controller/host/target. Some parts have been left untouched because they were sysfs entries and will probably end up being inaccurate if simply replaced here. Signed-off-by:
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Colin Ian King authored
The variable id len being initialized with a value that is never read, it is being re-assigned later on in a for-loop. The initialization is redundant and can be removed. Cleans up clang scan build warning: drivers/spi/spi-dw-dma.c:580:17: warning: Although the value stored to 'len' is used in the enclosing expression, the value is never actually read from 'len' [deadcode.DeadStores] Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Acked-by:
Serge Semin <fancer.lancer@gmail.com> Link: https://msgid.link/r/20240215131603.2062332-1-colin.i.king@gmail.comSigned-off-by:
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- 13 Feb, 2024 1 commit
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Dan Carpenter authored
Call pci_release_regions(pdev) before returning on this error path. Fixes: 3e7cfd6a ("spi: mchp-pci1xxxx: Add support for DMA in SPI") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Link: https://msgid.link/r/efc92197-4023-4bfe-bc63-452e7ed112e8@moroto.mountainSigned-off-by:
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- 09 Feb, 2024 1 commit
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Andy Shevchenko authored
In commit 8caab75f ("spi: Generalize SPI "master" to "controller"") some functions and struct members were renamed. Recent work by Uwe completes this renaming. However, there are plenty of leftovers in the comments and in-code documentation. Update them as well. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240209165423.2305493-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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- 08 Feb, 2024 31 commits
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Krzysztof Kozlowski authored
Use existing typedef for dma_filter_fn to avoid duplicating type definition. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240208202154.630336-3-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Add kerneldoc for dma_filter field in struct pl022_ssp_controller. Signed-off-by:
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Krzysztof Kozlowski authored
Use existing typedef for dma_filter_fn to avoid duplicating type definition. Signed-off-by:
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Mark Brown authored
Merge series from Tudor Ambarus <tudor.ambarus@linaro.org>: Various simple cleanups for the s3c64xx driver. Tested with gs101-spi.
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Mark Brown authored
Merge series from Uwe Kleine-König <u.kleine-koenig@pengutronix.de>: This series finishes off the removal of some of the legacy names for SPI controllers and devices.
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Mark Brown authored
Merge series from Tudor Ambarus <tudor.ambarus@linaro.org>: The Google GCS101 uses a variant of the Samsung SPI controller IP.
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Thangaraj Samynathan authored
pci1xxxx_spi_transfer_with_dma adds DMA support to copy the data between host cpu buffer and SPI IO Buffer. On DMA Completion interrupt, the next SPI transaction is initiated in isr. Helper functions pci1xxxx_spi_setup, pci1xxxx_spi_setup_dma_from_io, pci1xxxx_spi_setup_dma_to_io and pci1xxxx_start_spi_xfer are added for setting up spi, setting up dma operations, and to start spi transfer respectively. In the existing implementation, codes are replaced with helper functions wherever applicable. Signed-off-by:
Thangaraj Samynathan <thangaraj.s@microchip.com> Link: https://lore.kernel.org/r/20240207080621.30742-3-thangaraj.s@microchip.comSigned-off-by:
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Thangaraj Samynathan authored
In PCI1xxxx C0, support for DMA in PCIe endpoint is added to enhance the SPI performance. With this support, the performance is improved from 6Mbps to 17Mbps with 20Mhz clock. - DMA Supports two Channels, 0 and 1 - SPI Instance 0 uses chan 0 and SPI Instance 1 uses chan 1 - DMA can be used only if SPI is mapped to PF0 in the multi function endpoint and the MSI interrupt is supported - MSI interrupt of one of the SPI instance is assigned to the DMA and both channels 0 and 1 share the same irq, the MSI address and MSI Data of the irq is obtained and stored in DMA registers to generate interrupt Signed-off-by:
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Tudor Ambarus authored
Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Reviewed-by:
Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by:
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Tudor Ambarus authored
Allow SoCs that require 32 bits register accesses to write data in chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses is the google gs101. The operation is rare, thus open code it in the driver rather than making it generic (through asm-generic/io.h). Signed-off-by:
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Tudor Ambarus authored
There are SoCs (gs101) that allow only 32 bit register accesses. As the requirement is rare enough, for those SoCs we'll open code in the driver some s3c64xx_iowrite{8,16}_32_rep() accessors. Prepare for such addition. Suggested-by: -
Tudor Ambarus authored
Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Reviewed-by:
Peter Griffin <peter.griffin@linaro.org> Acked-by:
Andi Shyti <andi.shyti@kernel.org> Signed-off-by:
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Tudor Ambarus authored
val &= ~mask; val |= mask; is equivalent to: val |= mask; Drop the superfluous bitwise NOT operation. Reviewed-by:
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Tudor Ambarus authored
S3C64XX_SPI_TRAILCNT brings no benefit in terms of name over S3C64XX_SPI_MAX_TRAILCNT. Remove the duplicated definition. Reviewed-by:
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Tudor Ambarus authored
"samsung,spi-src-clk" and "num-cs" are optional dt properties. Downgrade the message from warning to debug message. Reviewed-by:
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Tudor Ambarus authored
Drop the blank line and move the logical operation in the body of the function rather than in initialization list. Reviewed-by:
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Tudor Ambarus authored
ETIMEDOUT is more specific than EIO, use it for wait_for_completion_timeout(). Reviewed-by:
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Tudor Ambarus authored
Don't monopolize the name. Prepend the driver prefix to the function name. Reviewed-by:
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Tudor Ambarus authored
DMA submit should just add the dma descriptor to a queue, without firing it. EIO is misleading and hides what happens in DMA. Propagate the dma_submit_error() error code, don't overwrite it. Signed-off-by:
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Tudor Ambarus authored
Check the return code of dmaengine_slave_config(). Reviewed-by:
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Tudor Ambarus authored
Move common code outside if else to avoid code duplication. Reviewed-by:
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Tudor Ambarus authored
Else case is not needed after a return, remove it. Reviewed-by:
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Tudor Ambarus authored
of_device_id::data is an opaque pointer. No explicit cast is needed. Remove unneeded (void *) casts in of_match_table. Reviewed-by:
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Tudor Ambarus authored
Fix typo, s/configuartion/configuration. Reviewed-by:
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Tudor Ambarus authored
The platform id is used as an index into the fifo_lvl_mask array. Platforms can come with a negative device ID, PLATFORM_DEVID_NONE (-1), thus we risked a negative array index. Catch such cases and fail to probe. Reviewed-by:
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Tudor Ambarus authored
The driver uses u32 and relies on an implicit inclusion of <linux/types.h>. It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Signed-off-by:
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Tudor Ambarus authored
The driver uses GENMASK() but does not include <linux/bits.h>. It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Reviewed-by:
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Tudor Ambarus authored
The driver uses readl() but does not include <linux/io.h>. It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Reviewed-by:
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Tudor Ambarus authored
Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Reviewed-by:
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Uwe Kleine-König authored
In commit 8caab75f ("spi: Generalize SPI "master" to "controller"") some functions and struct members were renamed. Adapt the documentation accordingly. Acked-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/3d643e22cacff12d3918ad5224baa1d01813d03b.1707324794.git.u.kleine-koenig@pengutronix.deSigned-off-by:
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Uwe Kleine-König authored
Now that all in-tree users followed the rename, the compat stuff can go away. This completes the renaming started with commit 8caab75f ("spi: Generalize SPI "master" to "controller"") Acked-by:
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