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  1. 21 Nov, 2019 6 commits
  3. 19 Nov, 2019 3 commits
    • Qianggui Song's avatar
      pinctrl: meson: add pinctrl driver support for Meson-A1 SoC · dabad1ff
      Qianggui Song authored 
      Meson A1 SoC share the same register layout of pinmux with previous
Meson-G12A, however there is difference for gpio and pin config register
in A1. The main difference is that registers before A1 are grouped by
function while those of A1 are by bank. The new register layout is as
below:

/* first bank */              /* addr */
- P_PADCTRL_GPIOP_I         base + 0x00 << 2
- P_PADCTRL_GPIOP_O         base + 0x01 << 2
- P_PADCTRL_GPIOP_OEN       base + 0x02 << 2
- P_PADCTRL_GPIOP_PULL_EN   base + 0x03 << 2
- P_PADCTRL_GPIOP_PULL_UP   base + 0x04 << 2
- P_PADCTRL_GPIOP_DS        base + 0x05 << 2

/* second bank */
- P_PADCTRL_GPIOB_I         base + 0x10 << 2
- P_PADCTRL_GPIOB_O         base + 0x11 << 2
- P_PADCTRL_GPIOB_OEN       base + 0x12 << 2
- P_PADCTRL_GPIOB_PULL_EN   base + 0x13 << 2
- P_PADCTRL_GPIOB_PULL_UP   base + 0x14 << 2
- P_PADCTRL_GPIOB_DS        base + 0x15 << 2

Each bank contains at least 6 registers to be configured, if one bank
has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included.
Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that
is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24
,0x25 according to above register layout. For previous chips, registers
are grouped according to their functions while registers of A1 are
according to bank.Also note that there is no AO bank any more in A1.

Current Meson pinctrl driver can cover such change by using base address
of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
make wrong value to reg_ds for Socs that do not support drive-strength
like AXG.To make things simple, add an extra dt parser function for
a1 and remain the old dt parser function for only reg parsing.
Signed-off-by: default avatarQianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.comReviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      dabad1ff
    • Qianggui Song's avatar
      pinctrl: meson: add a new callback for SoCs fixup · fd422964
      Qianggui Song authored 
      In meson_pinctrl_parse_dt, it contains two parts: reg parsing and
SoC relative fixup for AO. Several fixups in the same code make it hard
to maintain, so move all fixups to each SoC's callback and make
meson_pinctrl_parse_dt just do the reg parsing, separate these two
parts.Overview of all current Meson SoCs fixup is as below:

+------+--------------------------------------+--------------------------+
|      |                                      |                          |
| SoC  |                EE domain             |        AO domain         |
+------+--------------------------------------+--------------------------+
|m8    | parse regs:                          | parse regs:              |
|m8b   |   gpio,mux,pull,pull-enable(skip ds) |    gpio,mux,pull(skip ds)|
|gxl   | fixup:                               | fixup:                   |
|gxbb  |   no                                 |     pull-enable = pull;  |
|axg   |                                      |                          |
+------+--------------------------------------+--------------------------+
|g12a  | parse regs:                          | parse regs:              |
|sm1   |   gpio,mux,pull,pull-enable,ds       |   gpio,mux,ds            |
|      | fixup:                               | fixup:                   |
|      |   no                                 |   pull = gpio;           |
|      |                                      |   pull-enable = gpio;    |
+------+--------------------------------------+--------------------------+
|a1 or | parse regs:                                                     |
|later |  gpio/mux (without ao domain)                                   |
|SoCs  | fixup:                                                          |
|      |  pull = gpio; pull-enable = gpio; ds = gpio;                    |
+------+-----------------------------------------------------------------+
Since m8-axg share the same ao fixup, make a common function
meson8_aobus_parse_dt_extra to do the job.
Signed-off-by: default avatarQianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.comReviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      fd422964
    • Stephan Gerhold's avatar
      pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control · 58afa801
      Stephan Gerhold authored 
      Some devices do not make use of the CMD0/DAT0/DAT2 direction control
pins of the MMC/SD card 0 interface. In this case we should leave
those pins unconfigured.

A similar case already exists for "mc1_a_1" vs "mc1_a_2"
when the MC1_FBCLK pin is not used.

Add a new "mc0_a_2" pin group which is equal to "mc0_a_1" except
with the MC0_CMDDIR, MC0_DAT0DIR and MC0_DAT2DIR pins removed.
Signed-off-by: default avatarStephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191117205439.239211-1-stephan@gerhold.netSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      58afa801
  5. 13 Nov, 2019 3 commits
  7. 07 Nov, 2019 2 commits
  9. 05 Nov, 2019 7 commits
  11. 04 Nov, 2019 6 commits
  13. 03 Nov, 2019 2 commits
  15. 01 Nov, 2019 5 commits
  17. 30 Oct, 2019 6 commits
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