- 11 Dec, 2018 1 commit
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Uwe Kleine-König authored
This is just preparatory work which allows to move some initialisation that currently is done in the per transfer hook .config to an earlier point in time in the next few patches. There is no change in behaviour introduced by this patch. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 06 Dec, 2018 3 commits
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Tomer Maimon authored
Update the PSPI NPCM binding document of the spi aliases use to define the spi ID number. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Tomer Maimon authored
Align pspi send function code with the recieve function code, Also simplify the code a bit with early return. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Rob Herring authored
Convert string compares of DT node names to use of_node_name_eq helper instead. This removes direct access to the node name pointer. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 04 Dec, 2018 5 commits
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Mark Brown authored
Merge branch 'topic/3wire-gpio' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-4.21 mode conflict
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Jay Fang authored
The Hisilicon Hip08 platform, that uses ACPI, has this controller. Let's add ACPI support for DW SPI MMIO-based host. The ACPI ID used is "HISI0173" for the Designware SPI controller of Hisilicon Hip08 platform. Signed-off-by: Jay Fang <f.fangjian@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
Commit b36f09c3 ("dmaengine: Add transfer termination synchronization support") deprecated dmaengine_terminate_all() in favor of dmaengine_terminate_sync() and dmaengine_terminate_async() to avoid freeing resources used by the DMA callback before its execution has concluded. Commit de92436a ("dmaengine: bcm2835-dma: Use vchan_terminate_vdesc() instead of desc_free") amended the BCM2835 DMA driver with an implementation of ->device_synchronize(), which is a prerequisite for dmaengine_terminate_sync(). Thus, clients of the DMA driver (such as the BCM2835 SPI driver) may now be converted to the new API. It is generally desirable to use the _sync() variant except in atomic context. There is only a single occurrence where the BCM2835 SPI driver calls dmaengine_terminate_all() in atomic context and that is in bcm2835_spi_dma_done() (the RX DMA channel's callback) to terminate the TX DMA channel. The TX DMA channel doesn't have a callback (yet), hence it is safe to use the _async() variant there. Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
The RX and TX FIFO of the BCM2835 SPI master each accommodate 64 bytes (16 32-bit dwords). The CS register provides hints on their fill level: "Bit 19 RXR - RX FIFO needs Reading ([¾] full) 0 = RX FIFO is less than [¾] full (or not active TA = 0). 1 = RX FIFO is [¾] or more full. Cleared by reading sufficient data from the RX FIFO or setting TA to 0." "Bit 16 DONE - Transfer Done 0 = Transfer is in progress (or not active TA = 0). 1 = Transfer is complete. Cleared by writing more data to the TX FIFO or setting TA to 0." "If DONE is set [...], write up to 16 [dwords] to SPI_FIFO. [...] If RXR is set read 12 [dwords] data from SPI_FIFO." [Source: Pages 153, 154 and 158 of https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Note: The spec is missing the "¾" character, presumably due to copy-pasting from a different charset. It also incorrectly refers to 16 and 12 "bytes" instead of 32-bit dwords.] In short, the RXR bit indicates that 48 bytes can be read and the DONE bit indicates 64 bytes can be written. Leverage this knowledge to read or write bytes blindly to the FIFO, without polling whether data can be read or free space is available to write. Moreover, when a transfer is starting, the TX FIFO is known to be empty, likewise allowing a blind write of 64 bytes. This cuts the number of bus accesses in half if the fill level is known. Also, the (posted) write accesses can be pipelined on the AXI bus since they are no longer interleaved with (non-posted) reads. bcm2835_spi_transfer_one_poll() switches to interrupt mode when a time limit is exceeded by calling bcm2835_spi_transfer_one_irq(). The TX FIFO may contain data in this case, but is known to be empty when the function is called from bcm2835_spi_transfer_one(). Hence only blindly fill the TX FIFO in the latter case but not the former. Signed-off-by: Lukas Wunner <lukas@wunner.de> Tested-by: Eric Anholt <eric@anholt.net> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
Commit 3bd7f658 ("spi: bcm2835: Overcome sglist entry length limitation") was unfortunately merged even though submission of a refined version was imminent. Apply those refinements as an amendment: * Drop no longer needed #include <asm/page.h>. The lines requiring its inclusion were removed by the commit. * Change type of tx_spillover flag from bool to unsigned int for consistency with dma_pending flag and pursuant to Linus' dictum: https://lkml.org/lkml/2017/11/21/384 * In bcm2835_rd_fifo_count() do not check for bs->rx_buf != NULL. The function will never be called if that's the case. * Amend kerneldoc of bcm2835_wait_tx_fifo_empty() to prevent its use in situations where the function might spin forever. (In response to a review comment by Stefan Wahren.) * Sync only the cacheline containing the RX prologue back to memory, not the full first sglist entry. * Use sg_dma_address() and sg_dma_len() instead of referencing the sglist entry members directly. Seems to be the more common syntax in the tree, even for lvalues. Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 03 Dec, 2018 3 commits
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Yogesh Narayan Gaur authored
Add support for octal mode I/O data transfer in spi-mem framework. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Yogesh Narayan Gaur authored
Add flags for Octal mode I/O data transfer Required for the SPI controller which can do the data transfer (TX/RX) on 8 data lines e.g. NXP FlexSPI controller. SPI_TX_OCTAL: transmit with 8 wires SPI_RX_OCTAL: receive with 8 wires Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Randy Dunlap authored
Fix build errors when CONFIG_PINCTRL is not enabled. The header file <linux/pinctrl/consumer.h> handles both CONFIG_PINCTRL enabled and disabled cases. CC [M] drivers/spi/spi-at91-usart.o ../drivers/spi/spi-at91-usart.c: In function 'at91_usart_spi_runtime_suspend': ../drivers/spi/spi-at91-usart.c:409:2: error: implicit declaration of function 'pinctrl_pm_select_sleep_state' [-Werror=implicit-function-declaration] pinctrl_pm_select_sleep_state(dev); ../drivers/spi/spi-at91-usart.c: In function 'at91_usart_spi_runtime_resume': ../drivers/spi/spi-at91-usart.c:419:2: error: implicit declaration of function 'pinctrl_pm_select_default_state' [-Werror=implicit-function-declaration] pinctrl_pm_select_default_state(dev); Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Radu Pirea <radu.pirea@microchip.com> Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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- 29 Nov, 2018 3 commits
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Mark Brown authored
Make everything look intentional by having a C++ comment for the whole block, not just the SPDX line. Signed-off-by: Mark Brown <broonie@kernel.org>
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Mark Brown authored
Merge branch 'for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-4.21
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Lukas Wunner authored
Commit e82b0b38 ("spi: bcm2835: Fix race on DMA termination") broke the build with COMPILE_TEST=y on arches whose cmpxchg() requires 32-bit operands (xtensa, older arm ISAs). Fix by changing the dma_pending flag's type from bool to unsigned int. Fixes: e82b0b38 ("spi: bcm2835: Fix race on DMA termination") Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org>
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- 28 Nov, 2018 7 commits
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Lukas Wunner authored
When in DMA mode, the BCM2835 SPI controller requires that the FIFO is accessed in 4 byte chunks. This rule is not fulfilled if a transfer consists of multiple sglist entries, one per page, and the first entry starts in the middle of a page with an offset not a multiple of 4. The driver currently falls back to programmed I/O for such transfers, incurring a significant performance penalty. Overcome this hardware limitation by transferring the first few bytes of a transfer without DMA such that the remainder of the first sglist entry becomes a multiple of 4. Specifics are provided in kerneldoc comments. An alternative approach would have been to split transfers in the ->prepare_message hook, but this may necessitate two transfers per page, defeating the goal of clustering multiple pages together in a single transfer for efficiency. E.g. if the first TX sglist entry's length is 23 and the first RX's is 40, the first transfer would send and receive 23 bytes, the second 40 - 23 = 17 bytes, the third 4096 - 17 = 4079 bytes, the fourth 4096 - 4079 = 17 bytes and so on. In other words, O(n) transfers are necessary (n = number of sglist entries), whereas the algorithm implemented herein only requires O(1) additional work. Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
Document the driver's data structure to lower the barrier to entry for contributors. Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
Commit a30a555d ("spi: bcm2835: transform native-cs to gpio-cs on first spi_setup") disabled the use of hardware-controlled native Chip Select in favour of software-controlled GPIO Chip Select but left code to support the former untouched. Remove it to simplify the driver and ease the addition of new features and further optimizations. Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Mark Brown authored
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Lukas Wunner authored
If a DMA transfer finishes orderly right when spi_transfer_one_message() determines that it has timed out, the callbacks bcm2835_spi_dma_done() and bcm2835_spi_handle_err() race to call dmaengine_terminate_all(), potentially leading to double termination. Prevent by atomically changing the dma_pending flag before calling dmaengine_terminate_all(). Signed-off-by: Lukas Wunner <lukas@wunner.de> Fixes: 3ecd37ed ("spi: bcm2835: enable dma modes for transfers meeting certain conditions") Cc: stable@vger.kernel.org # v4.2+ Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
If submission of a DMA TX transfer succeeds but submission of the corresponding RX transfer does not, the BCM2835 SPI driver terminates the TX transfer but neglects to reset the dma_pending flag to false. Thus, if the next transfer uses interrupt mode (because it is shorter than BCM2835_SPI_DMA_MIN_LENGTH) and runs into a timeout, dmaengine_terminate_all() will be called both for TX (once more) and for RX (which was never started in the first place). Fix it. Signed-off-by: Lukas Wunner <lukas@wunner.de> Fixes: 3ecd37ed ("spi: bcm2835: enable dma modes for transfers meeting certain conditions") Cc: stable@vger.kernel.org # v4.2+ Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lukas Wunner authored
The IRQ handler bcm2835_spi_interrupt() first reads as much as possible from the RX FIFO, then writes as much as possible to the TX FIFO. Afterwards it decides whether the transfer is finished by checking if the TX FIFO is empty. If very few bytes were written to the TX FIFO, they may already have been transmitted by the time the FIFO's emptiness is checked. As a result, the transfer will be declared finished and the chip will be reset without reading the corresponding received bytes from the RX FIFO. The odds of this happening increase with a high clock frequency (such that the TX FIFO drains quickly) and either passing "threadirqs" on the command line or enabling CONFIG_PREEMPT_RT_BASE (such that the IRQ handler may be preempted between filling the TX FIFO and checking its emptiness). Fix by instead checking whether rx_len has reached zero, which means that the transfer has been received in full. This is also more efficient as it avoids one bus read access per interrupt. Note that bcm2835_spi_transfer_one_poll() likewise uses rx_len to determine whether the transfer has finished. Signed-off-by: Lukas Wunner <lukas@wunner.de> Fixes: e34ff011 ("spi: bcm2835: move to the transfer_one driver model") Cc: stable@vger.kernel.org # v4.1+ Cc: Mathias Duckeck <m.duckeck@kunbus.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 27 Nov, 2018 4 commits
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Leilk Liu authored
this patch add support for mt7629 IC. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Radu Pirea authored
This patch implements power management callback function for USART as SPI driver. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Signed-off-by: Mark Brown <broonie@kernel.org>
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Olof Johansson authored
The compiler has no way to know that rsize 1 or 2 are the only valid values. Also simplify the code a bit with early return. The warning was: drivers/spi/spi-npcm-pspi.c:215:6: warning: 'val' may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Mark Brown <broonie@kernel.org>
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Leilk Liu authored
This patch adds a DT binding documentation for the MT7629 soc. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 23 Nov, 2018 1 commit
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Dan Carpenter authored
There is an IS_ERR() vs PTR_ERR() typo here. The current code returns 1 but we want to return the negative error code. Fixes: 2a22f1b3 ("spi: npcm: add NPCM PSPI controller driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 17 Nov, 2018 1 commit
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Lubomir Rintel authored
A careless oversight. Sorry. Fixes: 0a897143b7c9 ("spi: pxa2xx: Add slave mode support") Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 16 Nov, 2018 2 commits
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Tony Lindgren authored
I've been wondering still about omap2-mcspi related suspend and resume flakeyness and looks like we're missing calls to spi_master_suspend() and spi_master_resume(). Adding those and using pm_runtime_force_suspend() and pm_runtime_force_resume() makes things work for suspend and resume and allows us to stop using noirq suspend and resume. And while at it, let's use SET_SYSTEM_SLEEP_PM_OPS to simplify things further. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Mark Brown authored
The refactoring done as part of adding the core support for handling waiting for slave transfer dropped a conditional which meant that we started waiting for completion of all transfers, not just those that the controller asked for. This caused hangs and massive delays on platforms that don't need the core delay. Re-add the delay to fix this. Fixes: 810923f3 (spi: Deal with slaves that return from transfer_one() unfinished) Reported-by: Tony Lindgren <tony@atomide.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 15 Nov, 2018 1 commit
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kbuild test robot authored
drivers/spi/spi-npcm-pspi.c:470:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: 2a22f1b3 ("spi: npcm: add NPCM PSPI controller driver") CC: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 14 Nov, 2018 2 commits
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Stefan Wahren authored
The license text is specifying GPL v2 or later but the MODULE_LICENSE is set to GPL v2 which means GNU Public License v2 only. So choose the license text as the correct one. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Florian Kauer <florian.kauer@koalo.de> Acked-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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Colin Ian King authored
The u32 variable csgpio is being checked for an error return from the call to of_get_named_gpio, however, since this is unsigned this comparison will always be false. Fix this by making csgpio an int and fix up the %u format specifiers to %d accordingly. Detected by CoverityScan, CID#1475476 ("Unsigned compared against 0") Fixes: 2a22f1b3 ("spi: npcm: add NPCM PSPI controller driver") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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- 13 Nov, 2018 7 commits
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Tomer Maimon authored
Add Nuvoton NPCM BMC Peripheral SPI controller driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Tomer Maimon authored
Added device tree binding documentation for Nuvoton BMC NPCM Peripheral SPI controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Fredrik Ternerot authored
Do not deselect cs when cs_change is set for the last transfer in the message. In this case, cs_change indicates that cs should stay selected until the next transfer. Signed-off-by: Fredrik Ternerot <fredrikt@axis.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lubomir Rintel authored
There doesn't seem to be a way to empty TXFIFO on MMP2. The datasheet is super-secret and the method described in Armada 16x manual won't work: "The TXFIFO and RXFIFO are cleared to 0b0 when the SSPx port is reset or disabled (by writing a 0b0 to the <Synchronous Serial Port Enable> field in the SSP Control Register 0)." # devmem 0xd4037008 # read SSSR 0x0000F204 # devmem 0xd4037000 32 0x07 # SSE off in SSCR0 # devmem 0xd4037000 32 0x87 # SSE on # devmem 0xd4037008 0x0000F204 ^ TXFIFO level is still 2. Sigh. The OLPC 1.75 boot firmware leaves two bytes in the TXFIFO. Those are basically throwaway bytes used in response to the messages from the EC. The OLPC kernel copes with this by power-cycling the hardware. Perhaps the firmware should do this instead. Other than that, there's not much we can do other than complain loudly until the garbage gets drained and discard the actual data... For the OLPC EC this will work just fine and pushing more data to TXFIFO would break further transactions. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lubomir Rintel authored
Strobe a GPIO line when the slave TX FIFO is filled. This is how the Embedded Controller on an OLPC XO-1.75 machine, that happens to be a SPI master, learns that it can initiate a transaction. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lubomir Rintel authored
This this is used to let the SPI master know that our FIFO is filled and we're ready to service a transfer. Only useful in slave mode. A signal like this is used by an embedded controller on a OLPC XO 1.75 machine, that happens to be a SPI master. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
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Lubomir Rintel authored
Tested on an OLPC XO-1.75 machine, where the Embedded Controller happens to be a SPI master. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Mark Brown <broonie@kernel.org>
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