- 05 Sep, 2005 40 commits
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Zachary Amsden authored
Subtle fix: load_TLS has been moved after saving %fs and %gs segments to avoid creating non-reversible segments. This could conceivably cause a bug if the kernel ever needed to save and restore fs/gs from the NMI handler. It currently does not, but this is the safest approach to avoiding fs/gs corruption. SMIs are safe, since SMI saves the descriptor hidden state. Signed-off-by:
Zachary Amsden <zach@vmware.com> Signed-off-by:
Andrew Morton <akpm@osdl.org> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Zachary Amsden authored
GCC can generate better code around descriptor update and access functions when there is not an explicit "eax" register constraint. Testing: You won't boot if this is messed up, since the TSS descriptor will be corrupted. Verified the assembler and booted. Signed-off-by:
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Zachary Amsden authored
i386 inline assembler cleanup. This change encapsulates descriptor and task register management. Also, it is possible to improve assembler generation in two cases; savesegment may store the value in a register instead of a memory location, which allows GCC to optimize stack variables into registers, and MOV MEM, SEG is always a 16-bit write to memory, making the casting in math-emu unnecessary. Signed-off-by:
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Zachary Amsden authored
i386 arch cleanup. Introduce the serialize macro to serialize processor state. Why the microcode update needs it I am not quite sure, since wrmsr() is already a serializing instruction, but it is a microcode update, so I will keep the semantic the same, since this could be a timing workaround. As far as I can tell, this has always been there since the original microcode update source. Signed-off-by:
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Zachary Amsden authored
i386 Inline asm cleanup. Use cr/dr accessor functions. Also, a potential bugfix. Also, some CR accessors really should be volatile. Reads from CR0 (numeric state may change in an exception handler), writes to CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it was not there to begin with, and in no case should kernel memory be clobbered, except when doing a TLB flush, which already has memory clobber. I noticed that page invalidation does not have a memory clobber. I can't find a bug as a result, but there is definitely a potential for a bug here: #define __flush_tlb_single(addr) \ __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) Signed-off-by: -
Roland McGrath authored
This makes the vDSO use nops for all its padding around instructions, rather than sometimes zeros, and nop-pads the end of the area containing instructions to a 32-byte cache line, to keep text and data in separate lines. Signed-off-by:
Roland McGrath <roland@redhat.com> Signed-off-by:
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Natalie.Protasevich@unisys.com authored
This is subarch update for ES7000. I've modified platform check code and removed unnecessary OEM table parsing for newer systems that don't use OEM information during boot. Parsing the table in fact is causing problems, and the platform doesn't get recognized. The patch only affects the ES7000 subach. Signed-off-by: <Natalie.Protasevich@unisys.com> Signed-off-by:
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Karsten Wiese authored
The VIA VT8237's IOAPIC sends 'APIC De-Assert Messages' by default, causing another CPU interrupt when the IRQ pin is de-asserted. This feature is switched off by the patch to get rid of doubled ioapic level interrupt rates. Signed-off-by:
Karsten Wiese <annabellesgarden@yahoo.de> Tested-by:
Ingo Molnar <mingo@elte.hu> Signed-off-by:
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Venkatesh Pallipadi authored
Signed-off-by:
Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by:
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Venkatesh Pallipadi authored
i386 generic subarchitecture requires explicit dmi strings or command line to enable bigsmp mode. The patch below removes that restriction, and uses bigsmp as soon as it finds more than 8 logical CPUs, Intel processors and xAPIC support. Signed-off-by:
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Vivek Goyal authored
o With introduction of kexec as boot-loader, the assumption that parameter segment will always be loaded at lower address than kernel and will be addressable by early bootup page tables is no longer valid. In kexec on panic case parameter segment might well be loaded beyond kernel image and might not be addressable by early boot page tables. o This case might hit in the scenario where user has reserved a chunk of memory for second kernel, for example 16MB to 64MB, and has also built second kernel for physical memory location 16MB. In this case kexec has no choice but to load the parameter segment at a higher address than new kernel image at safe location where new kernel does not stomp it. o Though problem should automatically go away once relocatable kernel for i386 is in place and kexec can determine the location of new kernel at run time and load parameter segment at lower address than kernel image. But till then this patch can go in (assuming it does not break something else). o This patch moves up the boot parameter saving code. Now boot parameters are copied out in protected mode before page tables are initialized. This will ensure that parameter segment is always addressable irrespective of its physical location. Signed-off-by:
Vivek Goyal <vgoyal@in.ibm.com> Signed-off-by:
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Petr Tesarik authored
If the virtual 86 machine reaches an instruction which raises a General Protection Fault (such as CLI or STI), the instruction is emulated (in handle_vm86_fault). However, the emulation ignored the TF bit, so the hardware debug interrupt was not invoked after such an emulated instruction (and the DOS debugger missed it). This patch fixes the problem by emulating the hardware debug interrupt as the last action before control is returned to the VM86 program. Signed-off-by:
Petr Tesarik <kernel@tesarici.cz> Signed-off-by:
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Matt Tolentino authored
The memory descriptors that comprise the EFI memory map are not fixed in stone such that the size could change in the future. This uses the memory descriptor size obtained from EFI to iterate over the memory map entries during boot. This enables the removal of an x86 specific pad (and ifdef) in the EFI header. I also couldn't stomach the broken up nature of the function to put EFI runtime calls into virtual mode any longer so I fixed that up a bit as well. For reference, this patch only impacts x86. Signed-off-by:
Matt Tolentino <matthew.e.tolentino@intel.com> Signed-off-by:
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Venkatesh Pallipadi authored
Only use read_timer_tsc only when CPU has TSC. Thanks to Andrea for pointing this out. Should not be issue on any platforms as all recent systems that has HPET also has CPUs that supports TSC. The patch is still required for correctness. Signed-off-by:
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Ingo Molnar authored
This patch pushes the creation of a rare signal frame (SIGBUS or SIGSEGV) into a separate function, thus saving stackspace in the main do_page_fault() stackframe. The effect is 132 bytes less of stack used by the typical do_page_fault() invocation - resulting in a denser cache-layout. (Another minor effect is that in case of kernel crashes that come from a pagefault, we add less space to the already existing frame, giving the crash functions a slightly higher chance to do their stuff without overflowing the stack.) (The changes also result in slightly cleaner code.) argument bugfix from "Guillaume C." <guichaz@gmail.com> Signed-off-by:
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Adrian Bunk authored
The LOG_BUF_SHIFT from lib/Kconfig.debug is sufficient. Signed-off-by:
Adrian Bunk <bunk@stusta.de> Acked-by:
Paul Mundt <lethal@Linux-SH.ORG> Signed-off-by:
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Ralf Baechle authored
Extend the compat mode kludgeology in envdev to cover MIPS as well. Or why we should need something like is_compat_task() ... Signed-off-by:
Ralf Baechle <ralf@linux-mips.org> Cc: Vojtech Pavlik <vojtech@suse.cz> Signed-off-by:
Dmitry Torokhov <dtor_core@ameritech.net> Signed-off-by:
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Yoichi Yuasa authored
vr41xx doesn't need mach-vr41xx/timex.h. This patch has removed mach-vr41xx/timex.h. Signed-off-by:
Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
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Yoichi Yuasa authored
This patch has fixed the following warnings. arch/mips/kernel/genex.S:250:5: warning: "CONFIG_64BIT" is not defined arch/mips/math-emu/cp1emu.c:1128:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:1206:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:1270:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:323:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:808:5: warning: "__mips64" is not defined arch/mips/math-emu/cp1emu.c:953:5: warning: "__mips64" is not defined arch/mips/mm/tlbex.c:519:5: warning: "CONFIG_64BIT" is not defined include/asm/reg.h:73:5: warning: "CONFIG_64BIT" is not defined Signed-off-by:
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Yoichi Yuasa authored
The addtion of SYS_SUPPORTS_*_KERNEL and CPU_SUPPORTS_*_KERNEL is halfway. This patch has added more SYS_SUPPORTS_*_KERNEL and CPU_SUPPORTS_*_KERNEL to arch/mips/Kconfig. Please apply. Signed-off-by:
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Yoichi Yuasa authored
This patch has added pcibios_bus_to_resource to MIPS. Signed-off-by:
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Yoichi Yuasa authored
Add pcibios_select_root to MIPS. Signed-off-by:
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Ralf Baechle authored
Fix the MIPS coherency configuration such that we always keep the mapping state in <asm/pci.h> when we need to on non-coherent platforms. Signed-off-by:
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Ralf Baechle authored
Signed-off-by:
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Ralf Baechle authored
Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by:
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Yoichi Yuasa authored
This patch has changed from VR41XX to VR4100 series in arch/mips/Kconfig. Signed-off-by:
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Yoichi Yuasa authored
This patch has removed obsolete VRC4171 config. Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
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Yoichi Yuasa authored
$ make menuconfig scripts/kconfig/mconf arch/i386/Kconfig drivers/char/Kconfig:847:warning: 'select' used by config symbol 'TANBAC_TB0219' refer to undefined symbol 'PCI_VR41XX' Here is a patch for this warning fix. Signed-off-by:
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Yoichi Yuasa authored
This patch has added default select configs for vr41xx. Signed-off-by:
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Yoichi Yuasa authored
This patch has added TANBAC VR4131 multichip module in arch/mips/Kconfig Signed-off-by:
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Ralf Baechle authored
- MIPS Denmark does no longer exist; the PCI vendor ID is now owned by MIPS Technologies. - Add ID for SOC-it, MIPS's system controller. Signed-off-by:
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Ralf Baechle authored
Add support for the virtual MIPS system that is emulated by Qemu. See http://www.linux-mips.org/wiki/Qemu for a detailed current status. Signed-off-by:
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Ralf Baechle authored
Revive HX frame buffer support for 2.6. Signed-off-by:
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Ralf Baechle authored
Rewrite PMAG BA frame buffer driver for 2.6. Acked-by:
Antonino Daplas <adaplas@pol.net> Signed-off-by:
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Ralf Baechle authored
Get it working again. Signed-off-by:
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Ralf Baechle authored
Remove the one file which managed to survive the removel of HP Laserjet support. Signed-off-by:
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Adrian Bunk authored
Signed-off-by:
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Yoichi Yuasa authored
We also need this patch for removing mips vr4181. Signed-off-by:
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Ralf Baechle authored
There seem to be no more users or interest in the NEC Osprey evaluation system for the NEC VR4181 SOC which is an old part anyway, so remove the code. More information on the Osprey can be found at http://www.linux-mips.org/wiki/Osprey. Signed-off-by:
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Yoichi Yuasa authored
This patch has changed system type name in proc for vr41xx. Signed-off-by:
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