- 13 Mar, 2018 38 commits
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Martin Blumenstingl authored
Amlogic Meson GXL and AXG SoCs come with a (host-only) dwc3 USB controller. To use this controller a clock has to be enabled and a reset line has to be pulsed. Enabling the clock works identical to other SoCs. However, the reset line has to be pulsed (using reset_control_reset) instead of using a level reset (reset_control_{assert,deassert}). Signed-off-by:Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
Felipe Balbi <felipe.balbi@linux.intel.com>
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Martin Blumenstingl authored
Some SoCs (such as Amlogic Meson GXL for example) share the reset line with other components (in case of the Meson GXL example there's a shared reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller). Additionally SoC implementations may prefer a reset pulse over level resets. For now this falls back to the old defaults, which are: - reset lines are exclusive - level resets are being used Signed-off-by:
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Martin Blumenstingl authored
Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB controller. This requires a clock to be enabled and a reset line to be pulsed to get the hardware into a known state. Add the documentation for this IP block, similar to "qcom,dwc3.txt". Signed-off-by:
Rob Herring <robh@kernel.org> Tested-by:
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Gustavo A. R. Silva authored
Assign true or false to boolean variables instead of an integer value. This issue was detected with the help of Coccinelle. Acked-by:
John Youn <johnyoun@synopsys.com> Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Grigor Tovmasyan authored
Added core state checking in dwc2_hsotg_ep_queue() function to make sure that application will submit requests only in L0 state. Signed-off-by:
Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by:
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Grigor Tovmasyan authored
Added call_gadget() function call when entering to L1 state to inform gadget that core is in L1 state. Did the same thing when exiting from L1 state to inform gadget that core is in L0 state. Signed-off-by:
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Sevak Arakelyan authored
Configure core in device mode to support LPM according to programming guide. Device will start giving valid responses for LPM tokens. After this patch device side LPM will start working. Signed-off-by:
Sevak Arakelyan <sevaka@synopsys.com> Signed-off-by:
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Sevak Arakelyan authored
Enable "LPM Transaction Received" interrupt for receive an interrupt when host will send LPM token. Signed-off-by:
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Sevak Arakelyan authored
This interrupt indicates that an LPM transaction was received on the USB bus. After getting this interrupt we are going from L0 state to L1 state. Signed-off-by:
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Sevak Arakelyan authored
Add a function which will be called if device is in L1 sleep state and Resume/Remote Wakeup Detected interrupt is asserted. Signed-off-by:
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Sevak Arakelyan authored
Add lpm, lpm_clock_gating, besl, hird_threshold_en and hird_threshold core parameters. These will indicate LPM and LPM Errata support as well as chosen L1 sleeping mode for the core and PHY. Signed-off-by:
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Sevak Arakelyan authored
Make field names of GLPMCFG register in definitions to be the same with the databook. Signed-off-by:
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Razmik Karapetyan authored
Backup PCGCCTL1 register when entering hibernation mode and restore it after exiting from hibernation, to keep active ACG feature. Signed-off-by:
Razmik Karapetyan <razmik@synopsys.com> Signed-off-by:
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Razmik Karapetyan authored
Added function for supporting Active Clock Gating functionality in the driver. PCGCCTL1 (Power and Clock Control) register will be used for controlling the core`s active clock gating feature, and the previously reserved 12th bit in GHWCFG4 now indicates that the controller supports the Dynamic Power Reduction (Active Clock Gating) during no traffic scenarios such as L0, idle, resume and suspend states. dwc2_enable_acg() function sets GATEEN bit in PCGCCTL1 register and enables ACG, if it supported. According to ACG functional specification, enabling of ACG feature in host mode done in host initialization, before turning Vbus on, specifically in dwc2_core_host_init function. Enabling of ACG feature in device mode done in device initialization, before clearing the SftDiscon bit in DCTL. This bit was cleared in dwc2_hsotg_core_connect() function.So dwc2_enable_acg() called before dwc2_core_connect() calls. Signed-off-by:
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Stefan Wahren authored
We better print an error in case probing of dwc2 fails on setting the DMA coherent mask. Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
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Ludovic Desroches authored
Use GPIO descriptors instead of relying on the old method. Include irq.h header since it is needed and was indirectly included through of_gpio.h. Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by:
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Ludovic Desroches authored
With the removal of AVR platforms, code related to platform stuff is useless. Signed-off-by:
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Grigor Tovmasyan authored
The maximum value that unsigned char can hold is 255, meanwhile the maximum value of interval is 2^(bIntervalMax-1)=2^15. Signed-off-by:
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Vardan Mikayelyan authored
The probe function doesn't properly handle errors. Fix it so that it properly handles cleanup. Acked-by:
Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by:
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Vardan Mikayelyan authored
After platform_device_add(), if we error out, we must do platform_device_unregister(), which also does the put. So lets move devm_kzalloc() to simplify error handling and avoid calling of platform_device_unregister(). Acked-by:
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Vardan Mikayelyan authored
Move usb_phy_generic_register() function call to the top, to simplify error handling. If this fails we can simply return instead of cleaning up. Acked-by:
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Vardan Mikayelyan authored
Use devm_kzalloc() and remove the unnecessary kfree(). Acked-by:
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Minas Harutyunyan authored
Before flushing fifos required to check AHB master state and lush when AHB master is in IDLE state. Acked-by:
Minas Harutyunyan <hminas@synopsys.com> Signed-off-by:
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Minas Harutyunyan authored
Added missing GUSBCFG programming in host mode, which fixes transaction errors issue on HiKey and Altera Cyclone V boards. These field even if was programmed in device mode (in function dwc2_hsotg_core_init_disconnected()) will be resetting to POR values after core soft reset applied. So, each time when switching to host mode required to set this field to correct value. Acked-by:
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Minas Harutyunyan authored
According databook in Buffer and External DMA mode non-split periodic channels can't be halted. Acked-by:
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Razmik Karapetyan authored
Removed unnecessary debug prints about DMA mode for host side from dwc2_gahbcfg_init() function. Acked-by:
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Grigor Tovmasyan authored
Deleted dwc2_hcd_dump_frrem() function, because it used undefined parameters from dwc2_hsotg structure. The function body was in #ifdef statement and was never compiled. Also removed that parameters from dwc2_hsotg structure, which were used only in dwc2_hcd_dump_frrem() function. And also delete dwc2_sample_frrem macro, because without dwc2_hcd_dump_frrem() function it's lose its purpose. Acked-by:
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Razmik Karapetyan authored
Renamed __orr32 and __bic32 function names to more descriptive dwc2_set_bit and dwc2_clear_bit respectively. Acked-by:
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Razmik Karapetyan authored
Disabled only unmasked endpoints based on DAINTMSK register. This will allow to minimize GINTSTS_GOUTNAKEFF interrupt handling. Acked-by:
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Razmik Karapetyan authored
In 'for' loop skipped masked and non-ISOC EPs. Also breaked 'for' loop after setting SGOUTNAK in DCTL,when one enabled EP was detected. This will allow to minimize incomplete ISOC OUT interrupt handling. Acked-by:
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Razmik Karapetyan authored
Disabled only that ISOC endpoints,for which interrupt bit was set in the DAINTMSK register. This will allow to minimize incomplete ISOC IN interrupt handling. Acked-by:
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Razmik Karapetyan authored
Changed AHB burst size from INCR4 to INCR by default. With this value driver shows excellent DMA performance. Acked-by:
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Razmik Karapetyan authored
In dwc2_hsotg_core_init_disconnected() function used AHB burst size parameter, instead of calculating already calculated value. Acked-by:
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Sevak Arakelyan authored
Move dwc2_hsotg_wait_bit_set function to core.c so it can be used anywhere in the code. Added dwc2_hsotg_wait_bit_clear function in core.c. Replace all the parts of register bit polling code with dwc2_hsotg_wait_bit_set or dwc2_hsotg_wait_bit_clear functions calls depends on code logic. Acked-by:
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Gevorg Sahakyan authored
Only check the ID portion of the GSNPSID register and don’t check the version. This will allow the driver to work with version 4.00a and later of the DWC_hsotg IP. Acked-by:
Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by:
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Lars-Peter Clausen authored
Some UDC drivers (like the DWC3) expect that the response to a setup() request is queued from within the setup function itself so that it is available as soon as setup() has completed. Upon receiving a setup request the function fs driver creates an event that is made available to userspace. And only once userspace has acknowledged that event the response to the setup request is queued. So it violates the requirement of those UDC drivers and random failures can be observed. This is basically a race condition and if userspace is able to read the event and queue the response fast enough all is good. But if it is not, for example because other processes are currently scheduled to run, the USB host that sent the setup request will observe an error. To avoid this the gadget framework provides the USB_GADGET_DELAYED_STATUS return code. If a setup() callback returns this value the UDC driver is aware that response is not yet available and can uses the appropriate methods to handle this case. Since in the case of function fs the response will never be available when the setup() function returns make sure that this status code is used. This fixed random occasional failures that were previously observed on a DWC3 based system under high system load. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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Lars-Peter Clausen authored
When using a AIO read() operation on the function FS gadget driver a URB is submitted asynchronously and on URB completion the received data is copied to the userspace buffer associated with the read operation. This is done from a kernel worker thread invoking copy_to_user() (through copy_to_iter()). And while the user space process memory is made available to the kernel thread using use_mm(), some architecture require in addition to this that the operation runs with USER_DS set. Otherwise the userspace memory access will fail. For example on ARM64 with Privileged Access Never (PAN) and User Access Override (UAO) enabled the following crash occurs. Internal error: Accessing user space memory with fs=KERNEL_DS: 9600004f [#1] SMP Modules linked in: CPU: 2 PID: 1636 Comm: kworker/2:1 Not tainted 4.9.0-04081-g8ab2dfb-dirty #487 Hardware name: ZynqMP ZCU102 Rev1.0 (DT) Workqueue: events ffs_user_copy_worker task: ffffffc87afc8080 task.stack: ffffffc87a00c000 PC is at __arch_copy_to_user+0x190/0x220 LR is at copy_to_iter+0x78/0x3c8 [...] [<ffffff800847b790>] __arch_copy_to_user+0x190/0x220 [<ffffff80086f25d8>] ffs_user_copy_worker+0x70/0x130 [<ffffff80080b8c64>] process_one_work+0x1dc/0x460 [<ffffff80080b8f38>] worker_thread+0x50/0x4b0 [<ffffff80080bf5a0>] kthread+0xd8/0xf0 [<ffffff8008083680>] ret_from_fork+0x10/0x50 Address this by placing a set_fs(USER_DS) before of the copy operation and revert it again once the copy operation has finished. This patch is analogous to commit d7ffde35 ("vhost: use USER_DS in vhost_worker thread") which addresses the same underlying issue. Signed-off-by:
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Thinh Nguyen authored
Increase max_speed of the mass_storage driver for UDCs that support SuperSpeed Plus. The composite driver will pass this value to UDC core to set the device speed on probe (actual speed may be different depending on whether the USB controller supports it or other external factors). Signed-off-by:
Thinh Nguyen <thinhn@synopsys.com> Signed-off-by:
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- 08 Mar, 2018 2 commits
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Chris Dickens authored
When the host wants to fetch OS descriptors, it sends two requests. The first is only for the header and the second for the full amount specified by the header in the first request. The OS descriptor handling code is distinguishing the header-only requests based on the wLength of the setup packet, but the same code is executed in both cases to construct the actual header. Simplify this by always constructing the header and then filling out the rest of the request if the wLength is greater than the size of the header. Also remove the duplicate code for queueing the request to ep0 by adding a goto label. Signed-off-by:
Chris Dickens <christopher.a.dickens@gmail.com> Signed-off-by:
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Chris Dickens authored
When handling an OS descriptor request, one of the first operations is to zero out the request buffer using the wLength from the setup packet. There is no bounds checking, so a wLength > 4096 would clobber memory adjacent to the request buffer. Fix this by taking the min of wLength and the request buffer length prior to the memset. While at it, define the buffer length in a header file so that magic numbers don't appear throughout the code. When returning data to the host, the data length should be the min of the wLength and the valid data we have to return. Currently we are returning wLength, thus requests for a wLength greater than the amount of data in the OS descriptor buffer would return invalid (albeit zero'd) data following the valid descriptor data. Fix this by counting the number of bytes when constructing the data and using this when determining the length of the request. Signed-off-by:
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