- 15 Jan, 2020 3 commits
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Reto Schneider authored
The radio module asserts CTS when its RX buffer has 10 bytes left. Putting just 8 instead of 16 bytes into the UART1 TX buffer on the Linux side ensures to not overflow the RX buffer on the radio module side. Signed-off-by:
Reto Schneider <reto.schneider@husqvarnagroup.com> Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Paul Burton <paul.burton@mips.com> Signed-off-by:
Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org
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Reto Schneider authored
This patch enables the WMAC controller on the GARDENA smart Gateway and configures the board specific factory EEPROM setting for this driver. Signed-off-by:
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Reto Schneider authored
This patch adds the WMAC controller description to the MT7628A dtsi file. Signed-off-by:
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- 13 Jan, 2020 2 commits
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Geert Uytterhoeven authored
Unlike its PCI counterpart, tc_match_device() was never used outside the TURBOchannel bus code. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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Geert Uytterhoeven authored
Unlike its PCI counterpart, gio_match_device() was never used outside the GIO bus code. Signed-off-by:
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- 10 Jan, 2020 4 commits
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Tiezhu Yang authored
If kzalloc fails, it should return -ENOMEM, otherwise may trigger a NULL pointer dereference. Fixes: 3adeb256 ("MIPS: Loongson: Improve LEFI firmware interface") Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
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Yangtao Li authored
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by:
Yangtao Li <tiny.windzz@gmail.com> Signed-off-by:
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Kees Cook authored
The FIELD_SIZEOF() macro was redundant, and is being removed from the kernel. Since commit c593642c ("treewide: Use sizeof_field() macro") this is one of the last users of the old macro, so replace it. Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Julia Lawall authored
Use resource_size rather than a verbose computation on the end and start fields. The semantic patch that makes these changes is as follows: (http://coccinelle.lip6.fr/) <smpl> @@ struct resource ptr; @@ - (ptr.end - ptr.start + 1) + resource_size(&ptr) </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by:
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- 09 Jan, 2020 29 commits
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Thomas Bogendoerfer authored
SGI IOC3 chip has integrated ethernet, keyboard and mouse interface. It also supports connecting a SuperIO chip for serial and parallel interfaces. IOC3 is used inside various SGI systemboards and add-on cards with different equipped external interfaces. Support for ethernet and serial interfaces were implemented inside the network driver. This patchset moves out the not network related parts to a new MFD driver, which takes care of card detection, setup of platform devices and interrupt distribution for the subdevices. Serial portion: Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-for-MFD-by:
Lee Jones <lee.jones@linaro.org> Network part: Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Network part: Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by:
Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by:
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Thomas Bogendoerfer authored
Our chosen byte swapping, which is what firmware already uses, is to do readl/writel by normal lw/sw intructions (data invariance). This also means we need to mangle addresses for u8 and u16 accesses. The mangling for 16bit has been done aready, but 8bit one was missing. Correcting this causes different addresses for accesses to the SuperIO and local bus of the IOC3 chip. This is fixed by changing byte order in ioc3 and m48rtc_rtc structs. Acked-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Thomas Bogendoerfer authored
Implented mapping of PCI INTB/C/D, which is needed for PCI multifunction devices, PCI-PCI bridges and IOC3. Signed-off-by:
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Thomas Bogendoerfer authored
per_cpu_init is called exactly once for every CPU. So there is no need for protection via slice_map. Signed-off-by:
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Thomas Bogendoerfer authored
Remember CPU speed while scanning for available CPUs to avoid looking it up a second time when printing CPU speed. Signed-off-by:
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Thomas Bogendoerfer authored
Reduce number of reserved interrupts by removing bits copied from IRIX and not used by Linux. Signed-off-by:
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Thomas Bogendoerfer authored
Move all IP27 declarations into one file. Signed-off-by:
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Thomas Bogendoerfer authored
IP35 has a different way to find out regions, so we move the IP27 implementation to IP27 specific file. Signed-off-by:
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Thomas Bogendoerfer authored
Convert printing of error status registers to use structs, which are defines for IP27 and IP35. Signed-off-by:
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Thomas Bogendoerfer authored
The upcoming header files for SGI-IP35 shouldn't add new typedef. To be able to share ip27-hubio.c we need to access register layouts no longer via a typedef. Signed-off-by:
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Thomas Bogendoerfer authored
SGI-IP35 uses slightly different memory layout, so we move IP27 defines to IP27 specific files and keep the common stuff in kldir.h Signed-off-by:
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Thomas Bogendoerfer authored
get_nasid() will be different for SGI-IP35, therefore move IP27 implementation to IP27 specific file. Signed-off-by:
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Thomas Bogendoerfer authored
Extracting node id from HUB register is specific to IP27 alias SN0. Move the macro definition to a SN0 header file. Signed-off-by:
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Thomas Bogendoerfer authored
The only piece needed in ip27.h is SEND_NMI. Move the define to the only place where it's used and remove ip27.h Signed-off-by:
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Thomas Bogendoerfer authored
By including agent.h where hub related defines/structs are needed, we have only one place to select, which agent chip (HUB or BEDROCK) is used. Signed-off-by:
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Thomas Bogendoerfer authored
By using cpu physid already present when scanning for CPUs get_cpu_slice() is unsued and can be removed together with two other then used functions. Signed-off-by:
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Thomas Bogendoerfer authored
Replication is done on a per node basis, so the use of cpumask was a misusage here. Signed-off-by:
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Paul Burton authored
Commit 716850ab ("MIPS: eBPF: Initial eBPF support for MIPS32 architecture.") enabled our eBPF JIT for MIPS32 kernels, whereas it has previously only been availailable for MIPS64. It was my understanding at the time that the BPF test suite was passing & JITing a comparable number of tests to our cBPF JIT [1], but it turns out that was not the case. The eBPF JIT has a number of problems on MIPS32: - Most notably various code paths still result in emission of MIPS64 instructions which will cause reserved instruction exceptions & kernel panics when run on MIPS32 CPUs. - The eBPF JIT doesn't account for differences between the O32 ABI used by MIPS32 kernels versus the N64 ABI used by MIPS64 kernels. Notably arguments beyond the first 4 are passed on the stack in O32, and this is entirely unhandled when JITing a BPF_CALL instruction. Stack space must be reserved for arguments even if they all fit in registers, and the callee is free to assume that stack space has been reserved for its use - with the eBPF JIT this is not the case, so calling any function can result in clobbering values on the stack & unpredictable behaviour. Function arguments in eBPF are always 64-bit values which is also entirely unhandled - the JIT still uses a single (32-bit) register per argument. As a result all function arguments are always passed incorrectly when JITing a BPF_CALL instruction, leading to kernel crashes or strange behavior. - The JIT attempts to bail our on use of ALU64 instructions or 64-bit memory access instructions. The code doing this at the start of build_one_insn() incorrectly checks whether BPF_OP() equals BPF_DW, when it should really be checking BPF_SIZE() & only doing so when BPF_CLASS() is one of BPF_{LD,LDX,ST,STX}. This results in false positives that cause more bailouts than intended, and that in turns hides some of the problems described above. - The kernel's cBPF->eBPF translation makes heavy use of 64-bit eBPF instructions that the MIPS32 eBPF JIT bails out on, leading to most cBPF programs not being JITed at all. Until these problems are resolved, revert the removal of the cBPF JIT performed by commit 716850ab ("MIPS: eBPF: Initial eBPF support for MIPS32 architecture."). Together with commit f8fffebd ("MIPS: BPF: Disable MIPS32 eBPF JIT") this restores MIPS32 BPF JIT behavior back to the same state it was prior to the introduction of the broken eBPF JIT support. [1] https://lore.kernel.org/linux-mips/MWHPR2201MB13583388481F01A422CE7D66D4410@MWHPR2201MB1358.namprd22.prod.outlook.com/Signed-off-by:
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Mao Wenan authored
There is no need to have the 'T *v' variable static since new value always be assigned before use it. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Mao Wenan <maowenan@huawei.com> Signed-off-by:
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Thomas Bogendoerfer authored
Implement placing of per_cpu into memory, which is local to the CPU. Signed-off-by:
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Thomas Bogendoerfer authored
Local node distance is defined as LOCAL_DISTANCE, which is 10. Use the define to give back correct local distance. Signed-off-by:
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Thomas Bogendoerfer authored
node_distance must return values starting from 10 up to 255. 10 means local, 255 unreachable. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Add X1830 system type for cat /proc/cpuinfo to give out X1830. 2.Change "PRID_IMP_XBURST" to "PRID_IMP_XBURST_REV1" and add a new "PRID_IMP_XBURST_REV2" for new Ingenic CPUs which has XBurst with MXU2 SIMD ISA. Notice: 1."PRID_IMP_XBURST_REV2" is corresponds to the latest XBurst processor with 128bit MXU2 SIMD instruction set, not the upcoming XBurst2 processor. This version of the processors fixes issues such as BTB and HPTLB. 2.In order to simplify and reuse the code, the "c->cputype" and the "c->writecombine" and the "__cpu_name[cpu]" in the original "PRID_IMP_XBURST" (now is "PRID_IMP_XBURST_REV1") are removed, and the corresponding settings are abtained through fall-through to "PRID_IMP_XBURST_REV2", which will cause the name that was previously mistakenly called "JZRISC" to become to the real name "XBurst". Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add a device tree for the Ingenic X1000 based YSH & ATIL CU Neo board. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> [paulburton@kernel.org: Drop stale mention of previously unselectable Kconfig entry.] Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Add Ingenic XBurst based boards, prepare for later dts. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
The "yna" is an acronym of the "YSH & ATIL". Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
Support the Ingenic X1000 SoC using the code under arch/mips/jz4740. This is left unselectable in Kconfig until a X1000 based board is added in a later commit. Signed-off-by:
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yu kuai authored
If of_find_device_by_node return 0 and ill_acc_of_setup return error, pdev don't have a corresponding object release. Fix it by adding put_device. Signed-off-by:
yu kuai <yukuai3@huawei.com> Signed-off-by:
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James Hogan authored
I haven't been active for 18 months, and Paul seems to be doing a grand job, so drop me from MIPS maintainership. Signed-off-by:
James Hogan <jhogan@kernel.org> Cc: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@vger.kernel.org Signed-off-by:
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- 05 Jan, 2020 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linuxLinus Torvalds authored
Pull RISC-V fixes from Paul Walmsley: "Several fixes for RISC-V: - Fix function graph trace support - Prefix the CSR IRQ_* macro names with "RV_", to avoid collisions with macros elsewhere in the Linux kernel tree named "IRQ_TIMER" - Use __pa_symbol() when computing the physical address of a kernel symbol, rather than __pa() - Mark the RISC-V port as supporting GCOV One DT addition: - Describe the L2 cache controller in the FU540 DT file One documentation update: - Add patch acceptance guideline documentation" * tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: Documentation: riscv: add patch acceptance guidelines riscv: prefix IRQ_ macro names with an RV_ namespace clocksource: riscv: add notrace to riscv_sched_clock riscv: ftrace: correct the condition logic in function graph tracer riscv: dts: Add DT support for SiFive L2 cache controller riscv: gcov: enable gcov for RISC-V riscv: mm: use __pa_symbol for kernel symbols
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