- 11 Jan, 2023 6 commits
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Konrad Dybcio authored
Enable the power and volume up buttons, connected to PON and RESIN respectively. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-6-konrad.dybcio@linaro.org
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Konrad Dybcio authored
Set up gpio-controlled fixed regulators for camera on PDX223 and fix up the existing ones in common and PDX224 trees. Signed-off-by:
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Konrad Dybcio authored
With PMIC GPIOs now available, set up required pin settings and add gpio-keys. Signed-off-by:
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX223&224 DTSIs to better document the hardware. Diff between 223 and 224: pm8350b < "CAM_PWR_LD_EN", > "NC", pm8350c < "RGBC_IR_PWR_EN", > "NC", Which is due to different camera power wiring on 223 and lack of a ToF sensor on 224. Signed-off-by:
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Konrad Dybcio authored
Now that SPMI is finally in place, include the DTSIs of PMICs present on Nagara. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Vinod Koul authored
Add the spmi bus as found in the SM8450 SoC Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list] Signed-off-by:
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- 10 Jan, 2023 21 commits
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Neil Armstrong authored
Add the QCE and Crypto BAM DMA nodes. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Add the I2C Master Hub wrapper and I2C serial engines nodes. Signed-off-by:
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Abel Vesa authored
Add dts file for Qualcomm MTP platform which uses SM8550 SoC. Co-developed-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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Neil Armstrong authored
Add nodes for PMR735d in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PMK8550 in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550vs in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550ve in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550b in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550 in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for pm8010 in separate dtsi file. Signed-off-by:
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Abel Vesa authored
Add base dtsi for SM8550 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, interconnect, thermal sensor, cpu cooling maps and SMMU nodes which helps boot to shell with console on boards with this SoC. Co-developed-by:
Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the TCSR clock binding, to gain the Devicetree include file.
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Abel Vesa authored
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Bjorn Andersson authored
Merge branch 'icc-sm8550-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3 Merge the immutable SM8550 interconnect branch, to gain the include file from the binding.
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Dmitry Baryshkov authored
Add silicon specific compatible qcom,sm8450-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8450 against the yaml documentation. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Add silicon specific compatible qcom,sm8150-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8150 against the yaml documentation. Signed-off-by:
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Krzysztof Kozlowski authored
Each board should define pin drive/bias for used busses. All boards using SPI0 (db845c and cheza) already do it, so drop the bias/drive strength from SoC DTSI. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by:
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Krzysztof Kozlowski authored
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: dd6459a0 ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Reported-by:
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Krzysztof Kozlowski authored
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: 89a32a4e ("arm64: dts: qcom: db845c: add analog audio support") Reported-by:
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Quentin Schulz authored
The reset line is active low for the Goodix touchscreen controller so let's fix the polarity in the Device Tree node. Signed-off-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com> Tested-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
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- 02 Jan, 2023 7 commits
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Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Soundwire is a bus and VA-macro requires a supply, thus both are expected to be explicitly enabled and populated by board DTS. The HDK8450 already enables Soundwire devices, except swr4 which as a result of this commit will stay disabled. Signed-off-by:
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- 29 Dec, 2022 6 commits
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Krzysztof Kozlowski authored
Node names should be generic so use consistently speaker-amp for CS35L41 speaker amplifier. Signed-off-by:
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Krzysztof Kozlowski authored
Bindings expect GCC clocks in other order: sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected Signed-off-by:
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Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-va-macro bindings nor the driver use "clock-frequency" property. Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and the bindings expect "bus" for simple-bus nodes: msm8996-mtp.dtb: agnoc@0: $nodename:0: 'agnoc@0' does not match '^bus(@[0-9a-f]+)?$' Signed-off-by:
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Marijn Suijten authored
Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware connected to them, leaving the rest disabled to save on power. For this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to be connected to Serial Engines on GPU DMA 1 / QUP 1. Beyond this downstream only defines a UART console available on Serial Engine 4 which also resides on QUP 0. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Martin Botka <martin.botka@somainline.org> Reviewed-by:
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Marijn Suijten authored
Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines. QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap in the middle (ranging from 5-9 with SPI 7 missing). Both QUPs have 5 I2C Serial Engines. [Marijn: Add iommus, reword patch description, reorder all properties, sort based on address, use QCOM_GPI_ constants, drop dma cells from 5 to 3] Signed-off-by:
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