- 18 Mar, 2022 40 commits
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Vamsi Krishna Gattupalli authored
This patch adds support to secure memory allocations for DSP. It repurposes the reserved field in struct fastrpc_invoke_args to add attributes to invoke request, for example to setup a secure memory map for dsp. Secure memory is assigned to DSP Virtual Machine IDs using Qualcomm SCM calls. Signed-off-by:
Vamsi Krishna Gattupalli <quic_vgattupa@quicinc.com> Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20220214161002.6831-9-srinivas.kandagatla@linaro.orgSigned-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Vamsi Krishna Gattupalli authored
Add fastrpc domain virtual machine IDs property. This property is used to setup memory protection for remote processor. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Jeya R authored
Reject session if DSP domain is secure, device node is non-secure and signed PD is requested. Secure device node can access DSP without any restriction. Unsigned PD offload is only allowed for the DSP domain that can support unsigned offloading. Signed-off-by:
Jeya R <jeyr@codeaurora.org> Signed-off-by:
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Srinivas Kandagatla authored
ADSP/MDSP/SDSP are by default secured, which means it can only be loaded with a Signed process. Where as CDSP can be either be secured/unsecured. non-secured Compute DSP would allow users to load unsigned process and run hexagon instructions, but blocking access to secured hardware within the DSP. Where as signed process with secure CDSP would be allowed to access all the dsp resources. This patch adds basic code to create device nodes as per device tree property. Signed-off-by:
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Jeya R authored
Add property to set DSP domain as non-secure. ADSP/MDSP/SDSP are by default secured, where as CDSP can be either be secured/unsecured. non-secured Compute DSP would allow users to load unsigned process and run hexagon instructions, but limiting access to secured hardware within the DSP. Based on this flag device nodes for secured and unsecured are created. Acked-by:
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Jeya R authored
Add support to get DSP capabilities. The capability information is cached on driver. Signed-off-by:
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Jeya R authored
Add support for IOCTL requests to map and unmap on DSP based on map flags. Signed-off-by:
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Srinivas Kandagatla authored
Currently fastrpc misc device instance is within channel context struct with a kref. So we have 2 structs with refcount, both of them managing the same channel context structure. Separate fastrpc device from channel context and by adding a dedicated fastrpc_device structure, this should clean the structures a bit and also help when adding secure device node support. Signed-off-by:
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Rafał Miłecki authored
NVRAM doesn't have cells at hardcoded addresses. They are stored in internal struct (custom & dynamic format). It's still important to define relevant cells in DT so NVMEM consumers can reference them. Update binding to allow including basic cells as NVMEM device subnodes. Reviewed-by:
Rafał Miłecki <rafal@milecki.pl> Signed-off-by:
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Rafał Miłecki authored
Most NVMEM providers have cells at hardcoded addresses however there are some exceptions. Some devices store cells layout in internal structs using custom formats. It's important to allow NVMEM consumers to still reference such NVMEM cells. Making "reg" optional allows defining NVMEM cells by their names only and using them with phandles. Reviewed-by:
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Rafał Miłecki authored
NVRAM consist of header and NUL separated key-value pairs. Parse it and create NVMEM cell for every key-value entry. Signed-off-by:
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Vincent Shih authored
1. Remove the unnecessary header file for dt-binding check 2. Replace OTPRX with 0x15 since it is not defined here. 3. Modify the name of the node of the clock driver. Fixes: 8fb29b45 ("dt-bindings: nvmem: Add bindings doc for Sunplus OCOTP driver") Reported-by:
Rob Herring <robh+dt@kernel.org> Signed-off-by:
Vincent Shih <vincent.sunplus@gmail.com> Signed-off-by:
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Markus Reichl authored
MAX31850 shares family number 0x3B with DS1825. The device is generally compatible with DS1825 but needs a different temperature readout. It operates always in 14 bit mode and has all 4 higher bits of the Config register set to 1. Conversion time is 100ms. Signed-off-by:
Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/20220306145817.8753-1-m.reichl@fivetechno.deSigned-off-by:
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Christian Vogel authored
Multiple pr_infos generate newlines, so the hexdump looks like... > 0x81: count=16, status: > 01 > 00 > 20 (...16 lines...) We switch to a single %*ph hexdump, using the built-in %ph format, which leads to this: [52769.348789] usb 2-1.3.1: Clearing ep0x83. [52769.349729] usb 2-1.3.1: ep_status=0x81, count=16,... ...status=01:00:20:40:05:04:04:00:20:53:00:00:00:00:00:00 Signed-off-by:
Christian Vogel <vogelchr@vogel.cx> Link: https://lore.kernel.org/r/20220311192833.1792-2-vogelchr@vogel.cxSigned-off-by:
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Tom Rix authored
Clang static analysis reports this representative problem counter-chrdev.c:482:3: warning: Undefined or garbage value returned to caller return ret; ^~~~~~~~~~ counter_get_data() has a multilevel switches, some without defaults, so ret is sometimes not set. Add returning -EINVAL similar to other defaults. Link: https://lore.kernel.org/r/20220227161746.82776-1-trix@redhat.comReviewed-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by:
Syed Nayyar Waris <syednwaris@gmail.com> Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
William Breathitt Gray <vilhelm.gray@gmail.com> Link: https://lore.kernel.org/r/b98d1a3ed4b0b324b261b23defd1bdddddba4d44.1647373009.git.vilhelm.gray@gmail.comSigned-off-by:
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William Breathitt Gray authored
The Counter subsystem tree is now separate from the IIO tree. Signed-off-by:
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Oleksij Rempel authored
Add counter_push_event() to notify user space about new pulses Link: https://lore.kernel.org/r/20220203135727.2374052-3-o.rempel@pengutronix.deSigned-off-by:
Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by:
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Oleksij Rempel authored
Add new counter event to notify user space about every new counter pulse. Link: https://lore.kernel.org/r/20220203135727.2374052-2-o.rempel@pengutronix.deSigned-off-by:
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William Breathitt Gray authored
Naming the counter device provides a convenient way to identify it in devres_log events and similar situations. This patch names the counter device by combining the prefix "counter" with the counter device's unique ID. Link: https://lore.kernel.org/r/20220204084551.16397-1-vilhelm.gray@gmail.comAcked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
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William Breathitt Gray authored
104_QUAD_8 depends on X86, but compiles fine on ARCH=arm. This patch adds support for COMPILE_TEST which is useful for compile testing code changes to the driver and Counter subsystem. Link: https://lore.kernel.org/r/20220105094137.259111-1-vilhelm.gray@gmail.com Cc: Syed Nayyar Waris <syednwaris@gmail.com> Suggested-by:
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Manivannan Sadhasivam authored
mhi_state_str[] array could be used by MHI endpoint stack also. So let's make the array as "static inline function" and move it inside the "common.h" header so that the endpoint stack could also make use of it. Reviewed-by:
Hemant Kumar <hemantk@codeaurora.org> Reviewed-by:
Alex Elder <elder@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-11-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Manivannan Sadhasivam authored
Move the common MHI definitions in host "internal.h" to "common.h" so that the endpoint code can make use of them. This also avoids duplicating the definitions in the endpoint stack. Reviewed-by:
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Manivannan Sadhasivam authored
Structure "struct mhi_tre" is representing a generic MHI ring element and not specifically a Transfer Ring Element (TRE). Fix the naming. Reviewed-by:
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Manivannan Sadhasivam authored
Cleanup includes: 1. Using the GENMASK macro for masks 2. Removing brackets for single values 3. Using lowercase for hex values 4. Using two digits for hex values where applicable 5. Aligning the defines on same column Reviewed-by:
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Manivannan Sadhasivam authored
Instead of using the hardcoded bits in DWORD definitions, let's use the bitfield operations to make it more clear how the DWORDs are structured. Suggested-by:
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Manivannan Sadhasivam authored
Functions like mhi_read_reg_field(), mhi_poll_reg_field() and mhi_write_reg_field() could be modified to not depend on the shift value passed as an argument. Instead, the bitfield operation could be used to extract the shift value from the mask itself. This eliminates the need to define _SHIFT (and _SHFT) macros and simplifies the code a bit. For shift values those cannot be determined during build time, "__ffs()" helper is used find the shift value during runtime. While at it, let's also get rid of 32-bit masks like CHDBOFF_CHDBOFF_MASK by doing the full 32-bit register read. Suggested-by:
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Manivannan Sadhasivam authored
In preparation of the endpoint MHI support, let's move the host MHI code to its own "host" directory and adjust the toplevel MHI Kconfig & Makefile. While at it, let's also move the "pci_generic" driver to "host" directory as it is a host MHI controller driver. Reviewed-by:
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Paul Davey authored
The MHI driver does not work on big endian architectures. The controller never transitions into mission mode. This appears to be due to the modem device expecting the various contexts and transfer rings to have fields in little endian order in memory, but the driver constructs them in native endianness. Fix MHI event, channel and command contexts and TRE handling macros to use explicit conversion to little endian. Mark fields in relevant structures as little endian to document this requirement. Fixes: a6e2e352 ("bus: mhi: core: Add support for PM state transitions") Fixes: 6cd330ae ("bus: mhi: core: Add support for ringing channel/event ring doorbells") Cc: stable@vger.kernel.org Reviewed-by:
Paul Davey <paul.davey@alliedtelesis.co.nz> Signed-off-by:
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Paul Davey authored
On big endian architectures the mhi debugfs files which report pm state give "Invalid State" for all states. This is caused by using find_last_bit which takes an unsigned long* while the state is passed in as an enum mhi_pm_state which will be of int size. Fix by using __fls to pass the value of state instead of find_last_bit. Also the current API expects "mhi_pm_state" enumerator as the function argument but the function only works with bitmasks. So as Alex suggested, let's change the argument to u32 to avoid confusion. Fixes: a6e2e352 ("bus: mhi: core: Add support for PM state transitions") Cc: stable@vger.kernel.org [mani: changed the function argument to u32] Reviewed-by:
Manivannan Sadhasivam <mani@kernel.org> Reviewed-by:
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Yonglin Tan authored
For default mechanism, the driver uses default MRU 3500 if mru_default is not initialized. The Qualcomm configured the MRU size to 32768 in the WWAN device FW. So, we align the driver setting with Qualcomm FW setting. Link: https://lore.kernel.org/r/MEYP282MB2374EE345DADDB591AFDA6AFFD2E9@MEYP282MB2374.AUSP282.PROD.OUTLOOK.COM Fixes: ac4bf60b ("bus: mhi: pci_generic: Introduce quectel EM1XXGR-L support") Cc: stable@vger.kernel.org Reviewed-by:
Yonglin Tan <yonglin.tan@outlook.com> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in an error message. Fix it. Acked-by:
Dimitri Sivanich <sivanich@hpe.com> Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20220315222253.2960047-1-colin.i.king@gmail.comSigned-off-by:
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Maciej W. Rozycki authored
Nowadays PC-style parallel ports come in the form of PCI and PCIe option cards and there are some combined parallel/serial option cards as well that we handle in the parport subsystem. There is nothing in particular that would prevent them from being used in any system equipped with PCI or PCIe connectivity, except that we do not permit the PARPORT_PC config option to be selected for platforms for which ARCH_MIGHT_HAVE_PC_PARPORT has not been set for. The only PCI platforms that actually can't make use of PC-style parallel port hardware are those newer PCIe systems that have no support for I/O cycles in the host bridge, required by such parallel ports. Notably, this includes the s390 arch, which has port I/O accessors that cause compilation warnings (promoted to errors with `-Werror'), and there are other cases such as the POWER9 PHB4 device, though this one has variable port I/O accessors that depend on the particular system. Also it is not clear whether the serial port side of devices enabled by PARPORT_SERIAL uses port I/O or MMIO. Finally Super I/O solutions are always either ISA or platform devices. Make the PARPORT_PC option selectable also for PCI systems then, except for the s390 arch, however limit the availability of PARPORT_PC_SUPERIO to platforms that enable ARCH_MIGHT_HAVE_PC_PARPORT. Update platforms accordingly for the required <asm/parport.h> header. Acked-by:
Sudip Mukherjee <sudipm.mukherjee@gmail.com> Signed-off-by:
Maciej W. Rozycki <macro@orcam.me.uk> Link: https://lore.kernel.org/r/alpine.DEB.2.21.2202141955550.34636@angie.orcam.me.ukSigned-off-by:
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Andy Shevchenko authored
Switch to use module_parport_driver() to reduce boilerplate code. Note, it doesn't matter when we check the module parameter. If it was writable we even would have more flexibility of changing it at runtime (when built-in the kernel) after this patch. Acked-by:
Rodolfo Giometti <giometti@enneenne.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220210134943.62026-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Lad Prabhakar authored
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220309202327.16627-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Desmond Yan authored
As bcm_vk driver is not the production driver for viper, remove its pci device id from table. Acked-by:
Scott Branden <scott.branden@broadcom.com> Signed-off-by:
Desmond Yan <desmond.yan@broadcom.com> Link: https://lore.kernel.org/r/20220302025340.25602-1-desmond.yan@broadcom.comSigned-off-by:
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Yang Li authored
Eliminate the follow smatch warning: drivers/misc/cardreader/rts5228.c:494 rts5228_extra_init_hw() warn: inconsistent indenting Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20220303020206.98911-1-yang.lee@linux.alibaba.comSigned-off-by:
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Xiaolong Huang authored
The vm_param and cpu_regs need to be freed via kfree() before return -EINVAL error. Fixes: 9c5137ae ("virt: acrn: Introduce VM management interfaces") Fixes: 2ad2aaee ("virt: acrn: Introduce an ioctl to set vCPU registers state") Signed-off-by:
Xiaolong Huang <butterflyhuangxx@gmail.com> Signed-off-by:
Fei Li <fei1.li@intel.com> Link: https://lore.kernel.org/r/20220308092047.1008409-1-butterflyhuangxx@gmail.comSigned-off-by:
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Yonghua Huang authored
acrn_vm_ram_map can't pin the user pages with VM_PFNMAP flag by calling get_user_pages_fast(), the PA(physical pages) may be mapped by kernel driver and set PFNMAP flag. This patch fixes logic to setup EPT mapping for PFN mapped RAM region by checking the memory attribute before adding EPT mapping for them. Fixes: 88f537d5 ("virt: acrn: Introduce EPT mapping management") Signed-off-by:
Yonghua Huang <yonghua.huang@intel.com> Signed-off-by:
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Sebastian Andrzej Siewior authored
acrn_irqfds_mutex is not used, never was. Remove acrn_irqfds_mutex. Fixes: aa3b483f ("virt: acrn: Introduce irqfd") Cc: Fei Li <fei1.li@intel.com> Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Link: https://lore.kernel.org/r/YidLo57Kw/u/cpA5@linutronix.deSigned-off-by:
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Haowen Bai authored
fixes coccinelle warning: drivers/virt/fsl_hypervisor.c:690:5-8: Unneeded variable: "ret". Return "0" on line 698 Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1646966331-16813-1-git-send-email-baihaowen@meizu.comSigned-off-by:
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