- 30 Mar, 2017 40 commits
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Huang Rui authored
Signed-off-by:
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Alex Deucher authored
The ring structure already has what we need. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Avoids passing around additional parameters during setup. Reviewed-by:
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Alex Deucher authored
Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by:
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Alex Deucher authored
It's required. Reviewed-by:
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Alex Deucher authored
It's required. Reviewed-by:
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Alex Deucher authored
To better match where they are used. Called from sw_init and sw_fini. Reviewed-by:
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Alex Deucher authored
Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Xiangliang Yu authored
For MM sriov, need use MMSCH to init engine and the init procedures are all saved in mm table. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Xiangliang Yu authored
For MM SRIOV, need to prepare MM table send send it to MMSCH to initial UVD & VCE engine. Create new header file for the structures. Signed-off-by:
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Xiangliang Yu authored
In order to not break SRIOV gfx development, will revert this patch after vce proved working. Signed-off-by:
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Xiangliang Yu authored
Allocate MM table for sriov device. Signed-off-by:
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Xiangliang Yu authored
Add new structure for MM table for multi media scheduler of sriov. Signed-off-by:
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Xiangliang Yu authored
disable uvd for sriov temporarily. Signed-off-by:
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Xiangliang Yu authored
VCE SRIOV need use doorbell and only works on VCN0 ring now Signed-off-by:
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Xiangliang Yu authored
For SRIOV, MM don't need to care about PG & CG, skip it. Signed-off-by:
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Monk Liu authored
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Alex Deucher authored
Enable virtual displays if the user has enabled them via the kernel command line. Useful in virtual or headless environments. Reviewed-by:
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Xiangliang Yu authored
VF need virtual dce, enable it if device is vf. Signed-off-by:
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Xiangliang Yu authored
If gpu device is vf, set virt ops so that guest can talk with GPU hypervisor. Signed-off-by:
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Xiangliang Yu authored
Implement mailbox protocol for AI so that guest vf can communicate with GPU hypervisor. Signed-off-by:
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Xiangliang Yu authored
If enable DPM for VF, always get lot of warn_slow_patch_null in dmesg and vf doesn't support DPM. Signed-off-by:
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Xiangliang Yu authored
two reasons: 1. there is a spinlock around; 2. vm register is pf/vf copy, vf can access via mmio safely. Signed-off-by:
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Xiangliang Yu authored
Bypass PSP block for VF device. Signed-off-by:
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Monk Liu authored
Rework sdma init to support SR-IOV. Signed-off-by:
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Monk Liu authored
one issue unresolved for RLC: rlc will go wrong completely if there is a soft_reset before RLC ucode loading. to workaround above issue, we can totally ignore RLC in guest driver side due to there was already full initialization on RLC side by GIM Signed-off-by:
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Xiangliang Yu authored
Insert ce meta prior to cntx_cntl and de follow it. Signed-off-by:
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Monk Liu authored
it is needed for virtualization v2: squash in wptr value fix Signed-off-by:
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Xiangliang Yu authored
Init kiq via cpu mmio and init kcq through kiq. Signed-off-by:
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Xiangliang Yu authored
Fullfill KIQ irq funcs to support kiq interrupt. v2: squash in adding interrupt src Signed-off-by:
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Xiangliang Yu authored
Fullfill kiq funcs to support kiq ring. v2: squash in 64bit ptr fix Signed-off-by:
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Xiangliang Yu authored
Allocate KIQ ring in sw_init for gfx9. Signed-off-by:
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Xiangliang Yu authored
Read vega10 hw register to detect if sriov is enabled, and call it before IP blocks setting. Signed-off-by:
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Monk Liu authored
Required for SR-IOV. Signed-off-by:
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Junwei Zhang authored
v2: add AMD_EXP_HW_SUPPORT for now Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Ken Wang authored
Acked-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
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Ken Wang authored
Add soc15 support and enable all the IPs for vega10. v2: squash in xclk fix v3: disable HDP MGCG Acked-by:
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Eric Huang authored
Adds power management support for vega10. v2: squash in fan control and led config fixes from Rex v3: squash in dead code removal and socvid fixes from Rex v4: squash in dpm force level fix from Rex v5: squash in latest headless, gpu load fixes from Rex Acked-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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