- 06 Dec, 2017 40 commits
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Arun Pandey authored
Signed-off-by:
Arun Pandey <Arun.Pandey@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tony Cheng authored
plane update prior to stream enablement is there to recombine pipe in case we need free pipe for new display. need to pass in new state or we will just re-applyingwhat we already have Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
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Andrew Jiang authored
This way, we can know exactly what triggered the update type we're looking at, and we can simplify the logic for determining what exactly needs to be updated in the future. Also allow a dst rect size increase to go through a medium update, since that does not require us to increase clock or bandwidth. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Andrew Jiang authored
We shouldn't be able to get a non-visible plane into DC anymore. Signed-off-by:
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Leo (Sunpeng) Li authored
The fail goto is incorrect. It will incorrectly release the dc_states on stream programming failure. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
This is a follow-up to the following change: Yongqiang Sun: Program front end first when set mode. Due to pipe-splitting features, how we handle stream enabling and disabling needs to change. In the case of pipe split disable, two planes need to be combined back into the same stream. This needs to be done before any stream programming happens. The previous patch addresses this, but breaks cross-platform compatibility. It's not guaranteed that a dc commit will be called separately to program planes and streams. Therefore, we handle the combined commit case by doing plane programming both before and after stream programming, to handle pipe split disable and plane enable respectively. Signed-off-by:
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Leo (Sunpeng) Li authored
When disabling pipe splitting, we need to make sure we disable both planes used. This should be done for Linux as well. Signed-off-by:
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Yongqiang Sun authored
In case of update type is medium, optimize squence, reduce programing time. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Roman Li authored
also simplifying syntax and removing unused variable in dce110_apply_ctx_for_surface() Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Yongqiang Sun authored
Power on one plane after disable all the planes, for a hw bug work around to resolve stutter efficiency issue. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Andrew Jiang authored
Make it so that differing dcc and plane size fields don't necessarily result in a full update, along with upscaling modes. This allows us to save some unnecessary full updates. Signed-off-by:
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Andrew Jiang authored
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Eric Yang authored
output signal used to be a public member to be used by DM to override the stream signal. Now since there is no longer separation between public and private part of stream, they are combined. The overriding was not working properly as well, which is addressed by this change Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by:
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Tony Cheng authored
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Eric Yang authored
Temporary solution to fix gamma adjustment not working. Signed-off-by:
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Yongqiang Sun authored
New scaler parameter assign to dpp is after early return, cause next flip scaler not program. Signed-off-by:
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Tony Cheng authored
Signed-off-by:
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Ken Chalmers authored
The ALLOW_SR registers might not always be available. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Hersen Wu authored
SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Yongqiang Sun authored
Optimized front end initial sequence, reset MPC module properly. Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
When new coefficients match cached we would skip setting regamma mode Also, when doing a stream update we would program regamma for all pipes, even thos that are not yet powered on. This resulted in never setting regamma since we would cache before the pipe is powered. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
Trying to align with kernel coding style and make it a bit more readable. Signed-off-by:
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Yongqiang Sun authored
There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by:
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Tony Cheng authored
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Tony Cheng authored
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Yue Hin Lau authored
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Eric Bernstein authored
Added a function to blank data using OPP DPG. Clean up code to prepare for pseudocode review with HW. Signed-off-by:
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Tony Cheng authored
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