- 19 Apr, 2024 6 commits
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Ahmad Rehman authored
In passthrough environment, the driver triggers the mode-1 reset on reload. The reset causes the core dump collection which is delayed task and prevents driver from unloading until it is completed. Since we do not need to collect data on "reset on reload" case, we can skip core dump collection. v2: Use the same flag to avoid calling amdgpu_reset_reg_dumps as well. Signed-off-by:
Ahmad Rehman <Ahmad.Rehman@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Sunil Khatri authored
Enable redirection of irq for pagefaults for specific clients to avoid overflow without dropping interrupts. So here we redirect the interrupts to another IH ring i.e ring1 where only these interrupts are processed. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Sunil Khatri authored
Add offsets, mask and shift macros for IH v6.0 which are needed to configure ring1 client irq redirection. Signed-off-by:
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Hawking Zhang authored
mode-2 reset is the only reliable method that can get GC/SDMA back when poison is consumed. mmhub requires mode-1 reset. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Sunil Khatri authored
We need IH ring1 for handling the pagefault interrupts which over flow in default ring for specific usecases. Signed-off-by:
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Sunil Khatri authored
We need IH ring1 for handling the pagefault interrupts which are overflowing the default ring for specific usecases. Signed-off-by:
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- 17 Apr, 2024 34 commits
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Alex Deucher authored
Convert a variable sized array from [1] to []. v2: fix up a few more. v3: integrate comments from Kees. Reviewed-by:
Kees Cook <keescook@chromium.org> Tested-by: Jeff Johnson <quic_jjohnson@quicinc.com> (v2) Acked-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by:
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Alex Deucher authored
The driver parses a union where the layout up through the first array is the same, however, the array has different sizes depending on the elements in the union. Be explicit to fix the UBSAN checker. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3323 Fixes: df8fc4e9 ("kbuild: Enable -fstrict-flex-arrays=3") Acked-by:
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Kenneth Feng authored
Support for smu ip block add for SMU v14. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Likun Gao authored
Add smu v14_0_2 ppt fucs support. v2: squash in updates (Alex) Signed-off-by:
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Likun Gao authored
Add initial support for smu v14_0_2. v2: fix warnings (Alex) v3: squash in various fixes (Alex) v4: squash in various fixes (Alex) v5: remove hardcoded pptable id (Alex) v6: update fw version (Alex) v7: squash in more updates (Alex) v8: rebase, squash in pptable override updates, combo table updates, SW CTF support (Alex) Signed-off-by: -
Likun Gao authored
Add pptable header for smu v14_0_2. Signed-off-by:
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Kenneth Feng authored
Add initial smu v14_0_2 ppsmc file v2: Squash in updates (Alex) v3: Squash in updates (Alex) Signed-off-by:
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Kenneth Feng authored
Add initial smu14 driver if file v2: squash in updates (Alex) v3: squash in updates (Alex) v4: squash in updates (Alex) Signed-off-by:
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Kenneth Feng authored
Add initial swSMU support for smu 14 series ASIC. v2: rebase (Alex) Signed-off-by:
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Hawking Zhang authored
Add a psp bl command enum for HAD_DRV. Signed-off-by:
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Ma Jun authored
refactor the code of runtime pm mode detection to support amdgpu_runtime_pm =2 and 1 two cases Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Hawking Zhang authored
while DBG_DRV is renamed to HAD_DRV for psp v14, part of its APIs/functionality is moved to a new component named Ipkeymgr_Drv. Signed-off-by:
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Thorsten Blum authored
s/,please/, please/ Reviewed-by:
Thorsten Blum <thorsten.blum@toblux.com> Signed-off-by:
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Rodrigo Siqueira authored
This reverts commit 002001b0. The original patch introduces cursor gamma issue to multiple Linux compositors. For this reason this commit reverts this change. Cc: Melissa Wen <mwen@igalia.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Ma Jun authored
Waiting for system ready to fix the discovery initialization failure issue. This failure usually occurs when dGPU is removed and then rescanned via command line. It's caused by following two errors: [1] vram size is 0 [2] wrong binary signature Signed-off-by:
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Christian König authored
When we removed the hacky start code check we actually didn't took into account that *all* VRAM pages needs to be CPU accessible. Clean up the code and unify the handling into a single helper which checks if the whole resource is CPU accessible. The only place where a partial check would make sense is during eviction, but that is neglitible. Signed-off-by:
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xinhui pan authored
Verify the parameters of amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place. Fixes: dc54d3d1 ("drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2") Cc: stable@vger.kernel.org Reported-by:
Vlad Stolyarov <hexed@google.com> Suggested-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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Yang Wang authored
add new aca smu callback parse_error_code{} to avoid specific asic check in amdgpu_aca.c file Signed-off-by: -
Aric Cyr authored
This version brings along following fixes: * Expand dmub_cmd operations. * Update DVI configuration. * Modify power sequence. * Enable Z10 flag for IPS. * Multiple code cleanups. Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Add some missing registers expansion in the dcn201_link_encoder file. Reviewed-by:
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Rodrigo Siqueira authored
Fill ring buffer before offload. Reviewed-by:
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Rodrigo Siqueira authored
This commit remove some unused code and also rename one of the define. Reviewed-by:
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Eric Bernstein authored
[Why] Update FMT_CONTROL settings based on HW spec [How] Update FMT settings for 4:2:0 Reviewed-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Jonathan Kim authored
MES internally has a timeout allowance of 2 seconds. Increase driver timeout to 3 seconds to be safe. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
This commit groups many parts of the code that are redundant or not used and drops all of them. Reviewed-by:
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Rodrigo Siqueira authored
This commit updates some comments to be more precise and adds another small comment to some other parts to improve the code readability. Reviewed-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
Move the scl_data.format to be close to other similar parts. Reviewed-by:
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Mikita Lipski authored
[why] Driver was passing a wrong command version which to DMCUB which caused the DMCUB to treat it as 0, so it wouldn't support dual eDP and would override the panel index to 0 instead of choosing between 0/1. [how] Use DMUB_CMD_PSR_CONTROL_VERSION_1 instead of PSR_VERSION_1. Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Ethan Bitnun authored
The previous assumption that there will be an optimize_bandwidth call following every prepare_bandwidth call was incorrect and caused small inaccuracies in logging, as some info was only updated in later prepare calls. Reviewed-by:
Ethan Bitnun <Ethan.Bitnun@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
Update headers by removing two unecessary headers and include a new one. Reviewed-by:
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Rodrigo Siqueira authored
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy way of dealing with chip ID. This commit uses dc_version instead of chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE. Signed-off-by:
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