- 25 Sep, 2020 40 commits
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Tianjia Zhang authored
This new module implement the SM2 public key algorithm. It was published by State Encryption Management Bureau, China. List of specifications for SM2 elliptic curve public key cryptography: * GM/T 0003.1-2012 * GM/T 0003.2-2012 * GM/T 0003.3-2012 * GM/T 0003.4-2012 * GM/T 0003.5-2012 IETF: https://tools.ietf.org/html/draft-shen-sm2-ecdsa-02 oscca: http://www.oscca.gov.cn/sca/xxgk/2010-12/17/content_1002386.shtml scctc: http://www.gmbz.org.cn/main/bzlb.htmlSigned-off-by:
Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Tested-by:
Xufeng Zhang <yunbo.xufeng@linux.alibaba.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Tianjia Zhang authored
The implementation of EC is introduced from libgcrypt as the basic algorithm of elliptic curve, which can be more perfectly integrated with MPI implementation. Some other algorithms will be developed based on mpi ecc, such as SM2. Signed-off-by:
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Tianjia Zhang authored
Expand the mpi library based on libgcrypt, and the ECC algorithm of mpi based on libgcrypt requires these functions. Some other algorithms will be developed based on mpi ecc, such as SM2. Signed-off-by:
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Tianjia Zhang authored
Both crypto_sm3_update and crypto_sm3_finup have been exported, exporting crypto_sm3_final, to avoid having to use crypto_sm3_finup(desc, NULL, 0, dgst) to calculate the hash in some cases. Signed-off-by:
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Weili Qian authored
'qm_init_qp_status' is just a help function to initiate some 'QP' status. 'QP' status should be updated separately. This patch removes the updating flags in 'QP' status. Signed-off-by:
Weili Qian <qianweili@huawei.com> Reviewed-by:
Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by:
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Yang Shen authored
The parameter type of 'pci_set_drvdata' is 'struct hisi_qm', so here the return type of 'pci_get_drvdata' should be 'struct hisi_qm' too. Signed-off-by:
Yang Shen <shenyang39@huawei.com> Signed-off-by:
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Meng Yu authored
Using 'g' not equal to 2 in dh algorithm may cause an error like this: arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: dh: Party A: generate public key test failed. err -22 11375.065672] dh alg: dh: test failed on vector 1, err=-22 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000080 hpre-dh self test failed arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000083 arm-smmu-v3 arm-smmu-v3.1.auto: 0x00000000000000c0 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000081 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000040 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000082 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000080 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 hisi_hpre 0000:79:00.0: dat_rd_poison_int_set [error status=0x8] found hisi_hpre 0000:79:00.0: ooo_rdrsp_err_int_set [error status=0xfc00] found hisi_hpre 0000:79:00.0: Controller resetting... hisi_hpre 0000:79:00.0: Controller reset complete {2}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0 {2}[Hardware Error]: event severity: recoverable {2}[Hardware Error]: Error 0, type: recoverable {2}[Hardware Error]: section type: unknown, c8b328a8-9917-4af6-9a13-2e08ab2e7586 {2}[Hardware Error]: section length: 0x4c as we missed initiating 'msg->in'. Fixes: c8b4b477("crypto: hisilicon - add HiSilicon HPRE accelerator") Signed-off-by:Meng Yu <yumeng18@huawei.com> Reviewed-by:
Zaibo Xu <xuzaibo@huawei.com> Signed-off-by:
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Meng Yu authored
Adjust some coding style to make code aligned. Signed-off-by:
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Meng Yu authored
1. Remove unused member 'debug_root' in 'struct hpre_debug'; 2. The u64 cast is redundant in 'cpu_to_le64'. Fixes: 84897415("crypto: hisilicon - Add debugfs for HPRE") Fixes: dadbe4c1("crypto: hisilicon/hpre - update debugfs ...") Signed-off-by:
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Colin Ian King authored
There is a statement that is indented by one whitespace too deeply, fix this by removing the whitespace. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Elena Petrova authored
Extend the user-space RNG interface: 1. Add entropy input via ALG_SET_DRBG_ENTROPY setsockopt option; 2. Add additional data input via sendmsg syscall. This allows DRBG to be tested with test vectors, for example for the purpose of CAVP testing, which otherwise isn't possible. To prevent erroneous use of entropy input, it is hidden under CRYPTO_USER_API_RNG_CAVP config option and requires CAP_SYS_ADMIN to succeed. Signed-off-by:
Elena Petrova <lenaptr@google.com> Acked-by:
Stephan Müller <smueller@chronox.de> Reviewed-by:
Eric Biggers <ebiggers@google.com> Signed-off-by:
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Corentin Labbe authored
This patch fixes the warning: warning: comparison of integer expressions of different signedness: 'int' and 'long unsigned int' [-Wsign-compare] Signed-off-by:
Corentin Labbe <clabbe@baylibre.com> Signed-off-by:
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Corentin Labbe authored
This patch fixes the warning: warning: comparison of integer expressions of different signedness: 'int' and 'long unsigned int' [-Wsign-compare] Signed-off-by:
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Corentin Labbe authored
This patch had support for the TRNG present in the CE. Note that according to the algorithm ID, 2 version of the TRNG exists, the first present in H3/H5/R40/A64 and the second present in H6. This patch adds support for both, but only the second is working reliabily according to rngtest. Signed-off-by:
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Corentin Labbe authored
This patch had support for the PRNG present in the CE. The output was tested with rngtest without any failure. Signed-off-by:
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Corentin Labbe authored
This patch adds a new stat_bytes counter in the sun8i-ce debugfs. Signed-off-by:
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Corentin Labbe authored
The CE support multiples hash algorithms, this patch adds support for MD5, SHA1, SHA224, SHA256, SHA384 and SHA512. Signed-off-by:
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Corentin Labbe authored
Hash algorithms will need also a spetial t_dlen handling, but since the meaning will be different, rename the current flag to specify it apply only on ciphers algorithms. Signed-off-by:
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Corentin Labbe authored
Error registers are different across SoCs. This patch handle those difference. Signed-off-by:
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Corentin Labbe authored
This patch split the do_one_request into three. Prepare will handle all DMA mapping and initialisation of the task structure. Unprepare will clean all DMA mapping. And the do_one_request will be limited to just executing the task. Signed-off-by:
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Corentin Labbe authored
Instead of storing IV data in the channel context, store them in the request context. Storing them in the channel structure was conceptualy wrong since they are per request related. Signed-off-by:
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Corentin Labbe authored
t_common_ctl is LE32 so we need to convert its value before using it. This value is only used on H6 (ignored on other SoCs) and not handling the endianness cause failure on xRNG/hashes operations on H6 when running BE. Fixes: 06f751b6 ("crypto: allwinner - Add sun8i-ce Crypto Engine") Signed-off-by:
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Corentin Labbe authored
This patch reworks the way debug info are printed. Instead of printing raw numbers, let's add a bit of context. Signed-off-by:
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Corentin Labbe authored
This patch adds some comment on structures used by sun8i-ss. Signed-off-by:
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Corentin Labbe authored
This fixes a trivial typo. Signed-off-by:
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Corentin Labbe authored
The SS support multiples hash algorithms, this patch adds support for MD5, SHA1, SHA224 and SHA256. Signed-off-by:
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Corentin Labbe authored
This patch had support for the PRNG present in the SS. The output was tested with rngtest without any failure. Signed-off-by:
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Corentin Labbe authored
Instead of using an hardcoded value, let's use a defined value for SS_START. Signed-off-by:
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Qinglang Miao authored
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by:
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Qinglang Miao authored
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by:
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Qinglang Miao authored
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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Qinglang Miao authored
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by:
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Qinglang Miao authored
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by:
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Corentin Labbe authored
Some line got only spaces, remove them Signed-off-by:
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Zhang Qilong authored
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by:
Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by:
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Ard Biesheuvel authored
Use the typed skcipher init/exit routines instead of the generic cra_init/_exit routines when instantiating/releasing the XTS skciphers. Signed-off-by:
Ard Biesheuvel <ardb@kernel.org> Signed-off-by:
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Ard Biesheuvel authored
Reordering the tweak is never necessary for encryption, so avoid the argument load on the encryption path. Signed-off-by:
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Ard Biesheuvel authored
Instead of using a homegrown macrofied version of the adr instruction that sets the Thumb bit in the output value, only to ensure that any bx instructions consuming that value will not switch out of Thumb mode when branching, use non-interworking mov (to PC) instructions, which achieve the same thing. Signed-off-by:
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Nicolas Toromanoff authored
If STM32 CRC device is already in use, calculate CRC by software. This will release CPU constraint for a concurrent access to the hardware, and avoid masking irqs during the whole block processing. Fixes: 7795c0ba ("crypto: stm32/crc32 - protect from concurrent accesses") Signed-off-by:
Nicolas Toromanoff <nicolas.toromanoff@st.com> Signed-off-by:
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Qinglang Miao authored
The mutex adf_ctl_lock is initialized statically. It is unnecessary to initialize by mutex_init(). Signed-off-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
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