- 10 Oct, 2022 4 commits
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Vladimir Stempen authored
[Why] Bandwidth validation is using Freesync parameters from previous Freesync state. Bandwidth validation ignores DCFCLK calculated after Freesync parameters are configured [How] Set Freesync bandwidth parameters to its default state before running bandwidth validation. Take DCFCLK calculated after Freesync bandwidth parameters are assigned and bandwidth is recalculated. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dillon Varone authored
This reverts commit e4e481e4. [Why & How] The reverted commit creates memory leak and causes issue upon driver install. Tested-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Request from PMFW to change the messaging format to specify whether we support z-state via individual bits. [How] Update the args we pass in the support message. Fixes: d5c6909e ("drm/amd/display: Add DCN314 clock manager") Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Shirish S authored
[Why] If psr_feature_enable is set to true by default, it continues to be enabled for non capable links. [How] explicitly disable the feature on links that are not capable of the same. Fixes: 8c322309 ("drm/amd/display: Enable PSR") Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
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- 06 Oct, 2022 36 commits
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Hamza Mahfooz authored
This reverts commit 66f99628. Unfortunately, that commit causes performance regressions on non-PSR setups. So, just revert it until FB_DAMAGE_CLIPS support can be added. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2189 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216554 Fixes: 66f99628 ("drm/amdgpu: use dirty framebuffer helper") Fixes: abbc7a3d ("drm/amdgpu: don't register a dirty callback for non-atomic") Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
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Philip Yang authored
amdkfd_total_mem_size is the size of total GPUs vram plus system memory to estimate page tables memory usage and leave enough VRAM room for page tables allocation. Calculate amdkfd_total_mem_size in amdgpu_amdkfd_device_probe is incorrect because adev->gmc.real_vram_size is still 0 called from amdgpu_device_ip_early_init. Move the calculation to amdgpu_amdkfd_device_init to get the correct VRAM size. Do reverse calculation in amdgpu_amdkfd_device_fini_sw to support hot-unplugging GPUs. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
Under VRAM usage pression, map to GPU may fail to create pt bo and vmbo->shadow_list is not initialized, then ttm_bo_release calling amdgpu_bo_vm_destroy to access vmbo->shadow_list generates below dmesg and NULL pointer access backtrace: Set vmbo destroy callback to amdgpu_bo_vm_destroy only after creating pt bo successfully, otherwise use default callback amdgpu_bo_destroy. amdgpu: amdgpu_vm_bo_update failed amdgpu: update_gpuvm_pte() failed amdgpu: Failed to map bo to gpuvm amdgpu 0000:43:00.0: amdgpu: Failed to map peer:0000:43:00.0 mem_domain:2 BUG: kernel NULL pointer dereference, address: RIP: 0010:amdgpu_bo_vm_destroy+0x4d/0x80 [amdgpu] Call Trace: <TASK> ttm_bo_release+0x207/0x320 [amdttm] amdttm_bo_init_reserved+0x1d6/0x210 [amdttm] amdgpu_bo_create+0x1ba/0x520 [amdgpu] amdgpu_bo_create_vm+0x3a/0x80 [amdgpu] amdgpu_vm_pt_create+0xde/0x270 [amdgpu] amdgpu_vm_ptes_update+0x63b/0x710 [amdgpu] amdgpu_vm_update_range+0x2e7/0x6e0 [amdgpu] amdgpu_vm_bo_update+0x2bd/0x600 [amdgpu] update_gpuvm_pte+0x160/0x420 [amdgpu] amdgpu_amdkfd_gpuvm_map_memory_to_gpu+0x313/0x1130 [amdgpu] kfd_ioctl_map_memory_to_gpu+0x115/0x390 [amdgpu] kfd_ioctl+0x24a/0x5b0 [amdgpu] Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
DRM buddy manager allocates the contiguous memory requests in a single block or multiple blocks. So for the ttm move operation (incase of low vram memory) we should consider all the blocks to compute the total memory size which compared with the struct ttm_resource num_pages in order to verify that the blocks are contiguous for the eviction process. v2: Added a Fixes tag v3: Rewrite the code to save a bit of calculations and variables (Christian) Fixes: c9cad937 ("drm/amdgpu: add drm buddy support to amdgpu") Signed-off-by:Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by:
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Yuan Can authored
After commit 5a8132b9 ("drm/amd/display: remove dead dc vbios code"), no one use struct i2c_id_config_access, so remove it. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Yuan Can <yuancan@huawei.com> Signed-off-by:
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Dong Chenchen authored
Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c: In function 'dcn31_hpo_dp_stream_enc_update_dp_info_packets': drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c:439:14: warning: variable 'sdp_stream_enable' set but not used [-Wunused-but-set-variable] 439 | bool sdp_stream_enable = false; Removed unused variable 'sdp_stream_enable'. Reviewed-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Dong Chenchen <dongchenchen2@huawei.com> Signed-off-by:
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Randy Dunlap authored
Rectify multiple kernel-doc warnings in dcn32_fpu.c. E.g.: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:247: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Finds dummy_latency_index when MCLK switching using firmware based drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:484: warning: Function parameter or member 'phantom_stream' not described in 'dcn32_set_phantom_stream_timing' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:601: warning: Function parameter or member 'dc' not described in 'dcn32_assign_subvp_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:601: warning: Function parameter or member 'context' not described in 'dcn32_assign_subvp_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:601: warning: Function parameter or member 'index' not described in 'dcn32_assign_subvp_pipe' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2140: warning: Function parameter or member 'dc' not described in 'dcn32_update_bw_bounding_box_fpu' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2140: warning: Function parameter or member 'bw_params' not described in 'dcn32_update_bw_bounding_box_fpu' drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.c:2140: warning: expecting prototype for dcn32_update_bw_bounding_box(). Prototype was for dcn32_update_bw_bounding_box_fpu() instead Reviewed-by:Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Yunxiang Li authored
manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on which causes drm_crtc_vblank_get in vrr_transition to fail, and later when drm_crtc_vblank_put is called the refcount on vblank will be messed up. Therefore move the call to after manage_dm_interrupts. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1247 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1380Tested-by:
Yunxiang Li <Yunxiang.Li@amd.com> Signed-off-by:
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Roman Li authored
[Why] DCN 3.1.4 supports DPIA. [How] - Set dpia_supported flag for dcn314 in dmub_hw_init() - Remove comment that becomes irrelevant after this change. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Ruili Ji authored
This patch is to fix the SDMA user queue doorbell missing issue on SDMA 6.0. F32_WPTR_POLL_ENABLE has to be set if doorbell mode is used. Otherwise ringing SDMA user queue doorbell can't wake up system from gfxoff. Signed-off-by:
Ruili Ji <ruiliji2@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Yang Yingliang authored
In some error path in amdgpu_sdma_init_microcode(), release_firmware() is not called, the memory allocated in request_firmware() will be leaked, calling amdgpu_sdma_destroy_inst_ctx() which calls release_firmware() to avoid memory leak. Fixes: 15aa1305 ("drm/amdgpu: add function to init SDMA microcode") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Signed-off-by:
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Yang Li authored
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2321Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yang Li authored
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2238Reported-by:
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Rodrigo Siqueira authored
This commit adds some minor code style changes just to reduce the merge conflicts we have when we upstream some of the VBA code. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Update DSC checks in the DCN32 VBA. Reviewed-by:
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Rodrigo Siqueira authored
[Why] During transition from ODM combine to ODM bypass, if DSC is enabled need to disconnect the DSC mux for pipes no longer in use. [How] During ODM update, detect pipes with DSC that are no longer being used for new state and call new DSC interface to disconnect. Add new DSC interface to disconnect from pipe Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Martin Leung authored
why and how: needed to fix bad assumption for enable mcm_luts Reviewed-by:
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Aric Cyr authored
This version brings along the following: - ILR improvements - PSR fixes - DCN315 fixes - DCN32 fixes - ODM fixes - DSC fixes - SubVP fixes Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
If the current configuration supports 2 to 1 ODM policy, let's also enable the windowed MPO feature. Reviewed-by:
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Rodrigo Siqueira authored
For some reason, we missed the PState check for DCN32 which may cause issues for clock transition. This commit add that required hook. Reviewed-by:
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Sonny Jiang authored
Enable VCN PG on GC11_0_1 Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Wenjing Liu authored
There is a missing register mask in dcn32 causing the hardware programming is not executed when programming SQ_num test pattern for DP2. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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George Shen authored
[Why] Certain features require the additional DP SDP configuration registers DP_SEC_CNTL1 and DP_SEC_CNTL5 in order to function correctly. The DCN32 DIO stream encoder reglist is currently missing these two registers. [How] Add the missing registers to the DCN32 DIO stream encoder reglist. Reviewed-by:
George Shen <George.Shen@amd.com> Signed-off-by:
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Eric Bernstein authored
[Why] In DIO stream encoder, definition of DP_DSC_MODE is changed (only enable/disable) In OPTC, OTG_SET_V_TOTAL_MIN_MASK_EN is removed (same as DCN3.1) [How] In DIO stream encoder, update enc32_dp_set_dsc_config(). In OPTC, use DCN3.1 version for function interfaces .set_vrr_m_const and .set_drr Reviewed-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW?] When merging ODM pipes that are using MPO, we must copy the stream_res from the new top pipe to the bottom pipe so that the overlayed plane is not pointing to the wrong stream assets. Reviewed-by:
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Rodrigo Siqueira authored
Add HDMI ACP bit field definition for DCN32. Reviewed-by:
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Rodrigo Siqueira authored
At some point, we decided to blank HUBP during pixel data blank, and to handle that, we added some OPTC lock checks. Later, we realized that this change caused multiple regression, and we removed it. Nevertheless, we still have some leftovers that might affect some ASIC behavior, and this commit drops those changes to keep the code consistent. Reviewed-by:
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Rodrigo Siqueira authored
SubVP has some issues related to how we allocate and enable it. This commit fixes this behavior by adding the proper check and configuration to the SubVP code path. Reviewed-by:
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Rodrigo Siqueira authored
DCN provides a hook to check if we can have a new pipe allocation based on some DC constraints. If the current configuration supports the new pipe request, DC updates its context; otherwise, it will keep the same configuration. This behavior is similar across multiple ASICs, and for this reason, we reused DCN20 on DCN321. However, this DCN32x has some peculiarities which require its function to avoid weird pipe split issues. This commit update this issue by using dcn32_acquire_idle_pipe_for_head_pipe_in_layer instead of dcn20_acquire_idle_pipe_for_layer. Reviewed-by:
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Rodrigo Siqueira authored
Under DCN32/321 we identified some code paths that DC never executes. This commit removes those unused codes to avoid distractions when debugging issues. Reviewed-by:
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Martin Leung authored
why: when dynamic odm was turned on, there is also logic to halve the pixelclk this still turned on when we avoided odm in the case of odd h_total timings how: block the pixel clk mechanism also in the case of odd h_total timings Reviewed-by:
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Aric Cyr authored
[how] Large deltas for periodic interrupts could result in the interrupt not being programmed properly and thus not firing. [why] Add proper wrap-around support for calculating VUPDATE and VLINE positions. Reviewed-by:
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Wenjing Liu authored
[why] According to specs, it expects us to write all 4 bytes even if current lane count is less than 4. Reviewed-by:
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Dillon Varone authored
[WHY?] Clocks are updating based on the incoming context's support, however the new compbuf size is not programmed prior to udpating clocks, which can result in P-State hangs. [HOW?] Increase compbuf size prior to updating clocks. Reviewed-by:
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Lewis Huang authored
[Why] Disable OTG when PSRSU with z10 even if z10 is disable [How] Reverse condition to keep OTG on when Z10 is disable Reviewed-by:
Robin Chen <po-tchen@amd.com> Acked-by:
Lewis Huang <Lewis.Huang@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
DCN315 has to always allow pstate change or SMU will hang. This workaround achieves this by applying a low pstate change latency to be used when pstate is calculated to be unsupported. This lower latency only accounts for memory retraining; a previous change handles locking in the highest available pstate allowing us to minimize required latency hiding to only account for memory retraining. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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