- 04 Oct, 2021 5 commits
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John Clements authored
clear error count when persistant harvesting is not enabled Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
[Why] For some reason we're defining DP 2.0 definitions inside our driver. Now that patches to introduce relevant definitions are slated to be merged into drm-next this is causing conflicts. In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here ^ 1 error generated. [How] Guard all display driver defines with #ifndef for now. Once we pull in the new definitions into amd-staging-drm-next we will follow up and drop definitions from our driver and provide follow-up header updates for any addition DP 2.0 definitions required by our driver. We also ensure drm_dp_helper.h is included before dc_dp_types.h. v3: Ensure drm_dp_helper.h is included before dc_dp_types.h v2: Add one missing endif Reviewed-by:Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Tao Zhou authored
In ras poison mode, page retirement will be handled by the irq handler of the module which consumes corrupted data. v2: rename ras_process_cb to ras_poison_consumption_handler. move the handler's implementation from ASIC specific file to common file. v3: call gpu reset for xGMI connected mode. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Prike Liang authored
In the s2idle stress test sdma resume fail occasionally,in the failed case GPU is in the gfxoff state.This issue may introduce by firmware miss handle doorbell S/R and now temporary fix the issue by forcing exit gfxoff for sdma resume. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Zhan Liu authored
[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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- 29 Sep, 2021 15 commits
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Zhan Liu authored
This patch is to add cyan_skillfish asic header files. Signed-off-by:
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Andrey Grodzovsky authored
To support libdrm tests. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Handle all DMA IOMMU group related dependencies before the group is removed and we try to access it after free. v2: Move the actul handling function to TTM Signed-off-by:
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Ernst Sjöstrand authored
We use the number_instance index that we get from the fw discovery blob to index into an array for example. Update error messages (Alex) Signed-off-by:
Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by:
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Arnd Bergmann authored
The two AMD drivers have their own custom offsetof() implementation that now triggers a warning with recent versions of clang: drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer subtraction with a null pointer has undefined behavior [-Werror,-Wnull-pointer-subtraction] Change all the instances to use the normal offsetof() provided by the kernel that does not have this problem. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Yang Li authored
Use resource_size function on resource object instead of explicit computation. Clean up coccicheck warning: ./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:905:10-13: ERROR: Missing resource_size with res Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reviewed-by:
Amos Kong <kongjianjun@gmail.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Arnd Bergmann authored
The overflow check in amdgpu_bo_list_create() causes a warning with clang-14 on 64-bit architectures, since the limit can never be exceeded. drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of comparison of constant 256204778801521549 with expression of type 'unsigned int' is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list)) ~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The check remains useful for 32-bit architectures, so just avoid the warning by using size_t as the type for the count. Fixes: 920990cb ("drm/amdgpu: allocate the bo_list array after the list") Reviewed-by: -
Simon Ser authored
On GFX9+, format modifiers are always enabled and ensure the frame-buffers can be scanned out at ADDFB2 time. On GFX8-, format modifiers are not supported and no other check is performed. This means ADDFB2 IOCTLs will succeed even if the tiling isn't supported for scan-out, and will result in garbage displayed on screen [1]. Fix this by adding a check for tiling flags for GFX8 and older. The check is taken from radeonsi in Mesa (see how is_displayable is populated in gfx6_compute_surface). Changes in v2: use drm_WARN_ONCE instead of drm_WARN (Michel) [1]: https://github.com/swaywm/wlroots/issues/3185Signed-off-by:
Simon Ser <contact@emersion.fr> Acked-by:
Michel Dänzer <mdaenzer@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Tom St Denis authored
The commit 2766534b added the offset header but didn't add the masks. This adds the masks based on what was selected for the offsets. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
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Charlene Liu authored
[why] pci deviceid not passed to dal dc, without proper break, dcn2.x falls into dcn3.x code path [how] pass in pci deviceid, and break once dal_version initialized. Reviewed-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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George Shen authored
[Why] Recently debugging efforts have involved setting/checking the X.Y value used during payload allocation. Current output for Y was calculated with incorrect bitshift. Y value is also not human readable. [How] Refactor logging into separate function. Fix Y calculation error and format output to be human readable. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why/How] Theoretically rare corner case where ceil(Y) results in rounding up to an integer. If this happens, the 1 should be carried over to the X value. Reviewed-by:
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Wenjing Liu authored
[why] There is a chance verified link cap can be greater than max link cap. This causes software hang because we cannot power up PHY with link rate that cannot handle. The change is to guard verfieid link cap from becoming larger than max link cap our PHy can support. Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
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Josip Pavic authored
[Why] Stack variable params.backlight_ramping_override is uninitialized, so it contains junk data [How] Initialize the variable to false Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Blnd, 3dlut, and shaper LUT select registers are double buffered, however their accompanying LUT memory shutdown registers are not. As a result, shutting down LUT memory immediately after setting a block to bypass causes corruption as bypass only happens at next Vupdate. [HOW] Re-enable mem low power for CM block Force optimization on next flip and disable LUT memory during optimization sequence if LUT select field is then set to bypass v2: squash in CONFIG_DRM_AMD_DC_DCN fix (Alex) Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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- 28 Sep, 2021 20 commits
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Qingqing Zhuo authored
[Why] DC should be used in place of DAL in upstream. [How] Replace dal with dc in function names. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: - Fixes to backlight, LUT, PPS, MST - Use correct vpg for 128b/132b encoding - Improved logging for VCP - Replace referral of dal with dc Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Oliver Logush authored
Reviewed-by:
Oliver Logush <oliver.logush@amd.com> Tested-by:
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Ilya authored
[Why] This change is needed for DCN2 to make use of the immediate_update flag. With this flag, update to PPS will be immediate, rather than always taking place on dig_update signal. [How] Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag value. Reviewed-by:
Ilya <Ilya.Bakoulin@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] MST streams share the same link and should share the same encoder. The current availability check may erroneously determine that an encoder is unavailable for MST streams. [How] When checking for link encoder availability, check if an encoder in use shares a link with the stream for which the availability check is being conducted. If the link is shared, then the link encoder should be shared too and will be deemed available. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] Link encoder in the link could be null for certain links. [How] If link encoder in the link is null then get the link encoder from the stream. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Wenjing Liu authored
[why] Unify the code which handles the conversion between hw lane setting and dpcd lane setting. v2: squash in unused variable fixes (Alex) Reviewed-by:
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Wenjing Liu authored
[why] To support per lane lane setting adjustment, we need to change cur_lane_setting to an array one for each lane as the first step. Reviewed-by:
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David Galiffi authored
[Why] Requested feature to assist with Thermal, Acoustic, Power, and Performance tuning. [How] Add a debug field that will override calculated minimum DRAM clock, if the debug value is larger than the calculate value. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
David Galiffi <David.Galiffi@amd.com> Tested-by:
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Eric Yang authored
[Why] To prevent unnecessary wake up of DMCUB when ABM is enabled without PSR enabled, driver will notify DMCUB to stop ABM's vertical interrupts if vsync is disabled and steady state is reached. [How] Send inbox message to notify ABM pause based on vsync on/off Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Michael Strauss authored
[WHY] AFMT is unused for DP audio, so powering it on for DP is unnecessary. [HOW] APG block should be powered down instead, however HW defaults to shutdown state when not enabled so no further work is required. Reviewed-by:
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Anthony Koo authored
Acked-by:
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Wenjing Liu authored
[why] 128b/132b uses the vpg instance assigned to hpo dp stream encoder. The current vpg used is assigned to dio stream encoder. This is incorrect and cause display black screen because the actual vpg is powered off. Reviewed-by:
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Hawking Zhang authored
didn't read the value of mmCP_HQD_QUANTUM from correct register offset Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Tao Zhou authored
In ras poison mode, umc uncorrectable error will be ignored until the corrupted data consumed by another ras module (such as gfx, sdma). v2: update the debug message and replace dev_warn with dev_info. Signed-off-by:
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Tao Zhou authored
Add RAS poison supported flag and tell PSP RAS TA about the info. v2: rename poison mode to poison supported, we can also disable poison mode even we support it. print value of poison supported if ras feature enablement fails. Signed-off-by: -
Tao Zhou authored
Add ras poison mode query interface for UMC. Signed-off-by:
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Tao Zhou authored
Add ras poison mode query interface for DF. v2: replace RREG32_PCIE with RREG32_SOC15. Signed-off-by:
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Candice Li authored
Updated invoke to use new common TA structure similarily to load/unload. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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