1. 31 Jan, 2017 1 commit
    • Catalin Marinas's avatar
      arm64: Improve detection of user/non-user mappings in set_pte(_at) · ec663d96
      Catalin Marinas authored
      Commit cab15ce6 ("arm64: Introduce execute-only page access
      permissions") allowed a valid user PTE to have the PTE_USER bit clear.
      As a consequence, the pte_valid_not_user() macro in set_pte() was
      replaced with pte_valid_global() under the assumption that only user
      pages have the nG bit set. EFI mappings, however, also have the nG bit
      set and set_pte() wrongly ignores issuing the DSB+ISB.
      
      This patch reinstates the pte_valid_not_user() macro and adds the
      PTE_UXN bit check since all kernel mappings have this bit set. For
      clarity, pte_exec() is renamed to pte_user_exec() as it only checks for
      the absence of PTE_UXN. Consequently, the user executable check in
      set_pte_at() drops the pte_ng() test since pte_user_exec() is
      sufficient.
      
      Fixes: cab15ce6 ("arm64: Introduce execute-only page access permissions")
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      ec663d96
  2. 27 Jan, 2017 3 commits
  3. 26 Jan, 2017 5 commits
  4. 23 Jan, 2017 1 commit
  5. 17 Jan, 2017 5 commits
    • Mark Rutland's avatar
      arm64: entry-ftrace.S: avoid open-coded {adr,ldr}_l · 829d2bd1
      Mark Rutland authored
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of these in entry-ftrace.S, removing open-coded
      sequences using adrp. This results in a minor code change, since a
      temporary register is not used when generating the address for some
      symbols, but this is fine, as the value of the temporary register is not
      used elsewhere.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      829d2bd1
    • Mark Rutland's avatar
      arm64: efi-entry.S: avoid open-coded adr_l · 526d10ae
      Mark Rutland authored
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of these in efi-entry.S, removing open-coded
      sequences using adrp.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Matt Fleming <matt@codeblueprint.co.uk>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      526d10ae
    • Mark Rutland's avatar
      arm64: head.S: avoid open-coded adr_l · 9bb00360
      Mark Rutland authored
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of adr_l these in head.S, removing an open-coded
      sequence using adrp.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9bb00360
    • Sudeep Holla's avatar
      arm64: cacheinfo: add support to override cache levels via device tree · 9a802431
      Sudeep Holla authored
      The cache hierarchy can be identified through Cache Level ID(CLIDR)
      architected system register. However in some cases it will provide
      only the number of cache levels that are integrated into the processor
      itself. In other words, it can't provide any information about the
      caches that are external and/or transparent.
      
      Some platforms require to export the information about all such external
      caches to the userspace applications via the sysfs interface.
      
      This patch adds support to override the cache levels using device tree
      to take such external non-architected caches into account.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Tested-by: default avatarTan Xiaojun <tanxiaojun@huawei.com>
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9a802431
    • Sudeep Holla's avatar
      of: base: add support to find the level of the last cache · 5fa23530
      Sudeep Holla authored
      It is useful to have helper function just to get the number of cache
      levels for a given logical cpu. We can obtain the same by just checking
      the level at which the last cache is present. This patch adds support
      to find the level of the last cache for a given cpu.
      
      It will be used on ARM64 platform where the device tree provides the
      information for the additional non-architected/transparent/external
      last level caches that are not integrated with the processors.
      
      Cc: Mark Rutland <mark.rutland@arm.com>
      Suggested-by: default avatarRob Herring <robh+dt@kernel.org>
      Acked-by: default avatarRob Herring <robh+dt@kernel.org>
      Tested-by: default avatarTan Xiaojun <tanxiaojun@huawei.com>
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      [will: use u32 instead of int for cache_level]
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      5fa23530
  6. 13 Jan, 2017 2 commits
  7. 12 Jan, 2017 9 commits
  8. 11 Jan, 2017 7 commits
  9. 10 Jan, 2017 7 commits