- 08 Feb, 2009 40 commits
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Paul Walmsley authored
This patch rolls up several cleanup patches. 1. Some unnecessarily verbose variable names are used in several clock.c functions; clean these up per CodingStyle. 2. Remove omap2_get_clksel() and just use clk->clksel_reg and clk->clksel_mask directly. 3. Get rid of void __iomem * usage in omap2_clksel_get_src_field. Prepend the function name with an underscore to highlight that it is a static function. linux-omap source commits are 7fa95e007ea2f3c4d0ecd2779d809756e7775894, af0ea23f1ee4a5bea3b026e38761b47089f9048a, and 91c0c979b47c44b08f80e4f8d4c990fb158d82c4. Signed-off-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Paul Walmsley authored
During _omap3_noncore_dpll_lock(), if a DPLL has no active downstream clocks and DPLL autoidle is enabled, the DPLL may never lock, since it will enter autoidle immediately. To resolve this, disable DPLL autoidle while locking the DPLL, and unconditionally wait for the DPLL to lock. This fixes some bugs where the kernel would hang when returning from retention or return the wrong rate for the DPLL. This patch is a collaboration with Peter de Schrijver <peter.de-schrijver@nokia.com> and Kevin Hilman <khilman@deeprootsystems.com>. linux-omap source commit is 3b7de4be879f1f4f55ae59882a5cbd80f6dcf0f0. Signed-off-by:
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Paul Walmsley authored
The DPLL FREQSEL jitter correction bits are set based on a table in the 34xx TRM, Table 4-38, according to the DPLL's internal clock frequency "Fint." Several Fint frequency ranges are missing from this table. Previously, we allowed these Fint frequency ranges to be selected in the rate rounding code, but did not change the FREQSEL bits. Correspondence with the OMAP hardware team indicates that Fint values not in the table should not be used. So, prevent them from being selected during DPLL rate rounding. This removes warnings and also can prevent the chip from locking up. The first pass through the rate rounding code will update the DPLL max and min dividers appropriately, so later rate rounding passes will run faster than the first. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9. Signed-off-by:
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Paul Walmsley authored
The previous DPLL rate rounding algorithm counted the divider (N) down from the maximum to 1. Since we currently use a broad DPLL rate tolerance, and lower N values are more power-efficient, we can often bypass several iterations through the loop by counting N upwards from 1. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is 6f6d82bb2f80fa20a841ac3e95a6f44a5a156188. Signed-off-by:
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Paul Walmsley authored
Remove some clutter from omap2_dpll_round_rate(). linux-omap source commit is 4625dceb8583c02a6d67ededc9f6a8347b6b8cb7. Signed-off-by:
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Paul Walmsley authored
Convert struct dpll_data.idlest_bit field to idlest_mask. Needed since OMAP2 uses two bits for DPLL IDLEST rather than one. While here, add the missing idlest_* fields for DPLL3. linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784 and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c. Signed-off-by:
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Paul Walmsley authored
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this into the OMAP3 clock framework. linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e. Signed-off-by:
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Paul Walmsley authored
Fix DPLL jitter correction programming. Previously, omap3_noncore_dpll_program() stored the FREQSEL jitter correction parameter to the wrong register. This caused jitter correction to be set incorrectly and also caused the DPLL divider to be programmed incorrectly. Also, fix DPLL divider programming. An off-by-one error existed in omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher divider than intended. linux-omap source commit is 5c0ec88a2145cdf2f2c9cc5fae49635c4c2476c7. Signed-off-by:
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Jouni Hogander authored
Using sdti doesn't keep emu_pwrdm on if hardware supervised pwrdm transitions are used. This causes sdti stop to work when power management is initialized and hardware supervised pwrdm control is enabled. This patch disables hardware supervised pwrdm control for emu_pwrdm. Now emu_pwrdm is switched off on boot by software when it is not used. Signed-off-by:
Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by:
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Paul Walmsley authored
Fix the clockdomain autodep code to respect omap_chip platform flags. Resolves "Unable to handle kernel paging request at virtual address 5f75706d" panic during power management initialization on OMAP2. Signed-off-by:
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Tomi Valkeinen authored
Enabling clock in a disabled power domain causes the power domain to be turned on. However, the power transition is not always finished when clk_enable() returns and this randomly crashes the kernel when an interrupt happens right after the clk_enable, and the kernel tries to read the irq status register for that domain. Why the irq status register is inaccessible, I don't know. Also it doesn't seem to be related to the module being not powered up, but to the transition itself. The same could perhaps happen after clk_disable also, but I have not witnessed that. The problem affects at least dss, cam and sgx clocks. This change waits for the transition to be finished before returning from omap2_clkdm_clk_enable(). Signed-off-by:
Tomi Valkeinen <tomi.valkeinen@nokia.com> Signed-off-by:
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Paul Walmsley authored
The SGX device on OMAP3 does not support retention, so remove RET from the list of possible SGX power states. Problem debugged by Richard Woodruff <r-woodruff2@ti.com>. Signed-off-by:
Richard Woodruff <r-woodruff2@ti.com> Signed-off-by:
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Paul Walmsley authored
Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and clockdomain; so, create powerdomain and clockdomain structures for them. Mark each DPLL clock as belonging to their respective DPLL clockdomain. cf. 34xx TRM Table 4-27 (among other references). linux-omap source commits are acdb615850b9b4f7d1ab68133a16be8c8c0e7419 and a8798a48f33e9268dcc7f30a4b4a3ce4220fe0c9. Signed-off-by:
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Paul Walmsley authored
sys_clkout2 belongs in the core_clkdm (3430 TRM section 4.7.2.2). It's not clear whether it actually is in the CORE clockdomain, or whether it is technically in a different clockdomain; but this is closer to reality than the present configuration. Signed-off-by:
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Paul Walmsley authored
Add clockdomains for the CM and PRM. These will ultimately replace the "wkup_clkdm", which appears to not actually exist on the hardware. Signed-off-by:
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Paul Walmsley authored
struct clockdomain contains a struct powerdomain *pwrdm and const char *pwrdm_name. The pwrdm_name is only used at initialization to look up the appropriate pwrdm pointer. Combining these into a union saves about 100 bytes on 3430SDP. This patch should not cause any change in kernel function. Updated to gracefully handle autodeps that contain invalid powerdomains, per Russell King's review comments. Boot-tested on BeagleBoard ES2.1. linux-omap source commit is 718fc6cd4db902aa2242a736cc3feb8744a4c71a. Signed-off-by:
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Kevin Hilman authored
This patch adds a CPUfreq frequency-table implementation for OMAP2 by walking the PRCM rate-table for available entries and adding them to a CPUfreq table. CPUfreq can then be used to manage switching between all the available entries in the PRCM rate table. Either use the CPUfreq sysfs interface directly, (see Section 3 of Documentation/cpu-freq/user-guide.txt) or use the cpufrequtils package: http://www.kernel.org/pub/linux/utils/kernel/cpufreq/cpufrequtils.htmlSigned-off-by:
Kevin Hilman <khilman@mvista.com> Updated to try to use cpufreq_table if it exists. linux-omap source commit is 77ce544fa48deb7a2003f454624e3ca10d37ab87. Signed-off-by:
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Paul Walmsley authored
Filling the set_rate and round_rate fields of dpll4_m4_ck makes this clock programmable through clk_set_rate(). This is needed to give omapfb control over the dss1_alwon_fck rate. This patch includes a fix from Tomi Valkeinen <tomi.valkeinen@nokia.com>. linux-omap source commits are e42218d45afbc3e654e289e021e6b80c657b16c2 and 9d211b761b3cdf7736602ecf7e68f8a298c13278. Signed-off-by:
Måns Rullgård <mans@mansr.com> Signed-off-by:
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Sergio Aguirre authored
Add CSI2 clock struct for handling it with clock API when TI PM is disabled. linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432. Signed-off-by:
Sergio Aguirre <saaguirre@ti.com> Acked-by:
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Daniel Stone authored
The GFX/SGX functional and interface clocks have different masks, for some unknown reason, so split EN_SGX_SHIFT into one each for fclk and iclk. Correct according to the TRM and the far more important 'does this actually work at all?' metric. linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e. Signed-off-by:
Daniel Stone <daniel.stone@nokia.com> Signed-off-by:
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Paul Walmsley authored
Fix some bugs in the OMAP3 clock tree pertaining to the 96MHz clocks. The 96MHz portion of the clock tree should now have reasonable fidelity to the 34xx TRM Rev I. One remaining question mark: it's not clear exactly which 96MHz source clock the USIM uses. This patch sticks with the previous setting, which seems reasonable. linux-omap source commit is 15c706e8179ce238c3ba70a25846a36b73bd2359. Signed-off-by:
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Paul Walmsley authored
Remove usbhost_sar_fclk from the OMAP3 clock framework. The bit that the clock was tweaking doesn't actually enable or disable a clock; it controls whether the hardware will save and restore USBHOST state when the powerdomain changes state. (That happens to coincidentally enable a clock for the duration of the operation, hence the earlier confusion.) In place of the clock, mark the USBHOST powerdomain as supporting hardware save-and-restore functionality. linux-omap source commit is f3ceac86a9d425d101d606d87a5af44afef27179. Signed-off-by:
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Paul Walmsley authored
This patch adds a missing OMAP24xx clock, the SSI L4 interface clock, as "ssi_l4_ick". linux-omap source commit is ace129d39b3107d330d4cf6934385d13521f2fec. Signed-off-by:
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Paul Walmsley authored
Fix sparse & checkpatch warnings in OMAP2/3 PRCM & PM code. This mostly consists of: - converting pointer comparisons to integers in form similar to (ptr == 0) to the standard idiom (!ptr) - labeling a few non-static private functions as static - adding prototypes for *_init() functions in the appropriate header files, and getting rid of the corresponding open-coded extern prototypes in other C files - renaming the variable 'sclk' in mach-omap2/clock.c:omap2_get_apll_clkin to avoid shadowing an earlier declaration Clean up checkpatch issues. This mostly involves: - converting some asm/ includes to linux/ includes - cleaning up some whitespace - getting rid of braces for conditionals with single following statements Also take care of a few odds and ends, including: - getting rid of unlikely() and likely() - none of this code is particularly fast-path code, so the performance impact seems slim; and some of those likely() and unlikely() indicators are probably not as accurate as the ARM's branch predictor - removing some superfluous casts linux-omap source commit is 347df59f5d20fdf905afbc26b1328b0e28a8a01b. Signed-off-by:
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Paul Walmsley authored
Add non-CORE DPLL rate set code and M,N programming for OMAP3. Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework. You may see some warnings on rate sets from the freqsel code. The table that TI presented in the 3430 TRM Rev F does not cover Fint < 750000, which definitely occurs in practice. However, the lack of this freqsel case does not appear to impair the DPLL rate change. linux-omap source commit is 689fe67c6d1ad8f52f7f7b139a3274b79bf3e784. Signed-off-by:
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Russell King authored
... rather than the clock names themselves. Signed-off-by: -
Russell King authored
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Russell King authored
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Russell King authored
... which now means no driver requests the "armxor_ck" clock directly. Also, fix the error handling for clk_get(), ensuring that we propagate the error returned from clk_get(). Signed-off-by: -
Russell King authored
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Russell King authored
By providing a dummy ick for OMAP1510 and OMAP310, we avoid having SoC conditional clock information in i2c-omap.c. Also, fix the error handling by making sure we propagate the error returned via clk_get(). Signed-off-by: -
Russell King authored
On OMAP1, the I2C functional clock (fck) is the armxor_ck, so there's no need to get "armxor_ck" separately. Signed-off-by: -
Russell King authored
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Russell King authored
Rather than introducing a special 'mcbsp_clk' with code behind it in mach-omap*/mcbsp.c to handle the SoC specifics, arrange for the mcbsp driver to be like any other driver. mcbsp requests its fck and ick clocks directly, and the SoC specific code deals with selecting the correct clock. There is one oddity to deal with - OMAP1 fiddles with the DSP clocks and DSP reset, so we move this to the two callback functions. Signed-off-by: -
Russell King authored
... rather than the clock names themselves. Signed-off-by: -
Russell King authored
Eliminate the OMAP1 vs OMAP2 clock knowledge in the MMC driver. Signed-off-by: -
Russell King authored
Convert OMAP MMC driver to match clocks using the device ID and a connection ID rather than a clock name. This allows us to eliminate the OMAP1/OMAP2 differences for the function clock. Signed-off-by: -
Russell King authored
Eliminate the OMAP1 vs OMAP2 clock knowledge in the watchdog driver. Signed-off-by: -
Russell King authored
This eliminates the need for separate OMAP24xx and OMAP34xx clock requesting code sections. Signed-off-by: -
Russell King authored
By providing a dummy clock node, we can eliminate the SoC conditional clock handing in the OMAP drivers, moving this knowledge out of the driver and into the machine clock support code. Signed-off-by:
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