1. 22 Feb, 2010 1 commit
    • Li Peng's avatar
      drm/i915: enable memory self refresh on 9xx · ee980b80
      Li Peng authored
      Enabling memory self refresh (SR) on 9xx needs to set additional
      register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the
      write to self refresh bit and bit 16 to enable the write of self
      refresh watermark. On 915, bit 12 of INSTPM is used to enable SR.
      
      SR will take effect when CPU enters C3+ state and its entry/exit
      should be automatically controlled by H/W, driver only needs to set
      SR enable bits in wm update. But this isn't safe in my test on 945
      because GPU is hung. So this patch explicitly enables SR when GPU
      is idle, and disables SR when it is busy. In my test on a netbook of
      945GSE chipset, it saves about 0.8W idle power.
      Signed-off-by: default avatarLi Peng <peng.li@intel.com>
      [anholt: rebased against 33c5fd12
      by adding disable of INSTPM SR bit on 915GM for two pipe setup]
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
      ee980b80
  2. 16 Feb, 2010 3 commits
  3. 12 Feb, 2010 12 commits
  4. 11 Feb, 2010 24 commits