- 14 Nov, 2017 11 commits
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Stephen Boyd authored
* clk-imx: clk: imx: imx7d: Remove ARM_M0 clock clk: imx: imx7d: Fix parent clock for OCRAM_CLK clk: imx: clk-imx6ul: allow lcdif_pre_sel to change parent rate clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPU
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Stephen Boyd authored
* clk-qcom: clk: qcom: clk-smd-rpm: add msm8996 rpmclks clk: qcom: Implement RPM clocks for MSM8660/APQ8060 clk: qcom: Update DT bindings for the MSM8660/APQ8060 RPMCC clk: qcom: Elaborate on "active" clocks in the RPM clock bindings clk: qcom: Remove unused RCG ops
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Stephen Boyd authored
* clk-at91: clk: at91: utmi: set the mainck rate
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Stephen Boyd authored
* clk-devm-provider: clk: qcom: common: Migrate to devm_* APIs for resets and clk providers clk: Add devm_of_clk_add_hw_provider()/del_provider() APIs
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Stephen Boyd authored
* clk-const: clk: make clk_init_data const clk: imx: make clk_ops const clk: mmp: make clk_ops const clk: hisilicon: make clk_ops const clk: mxs: make clk_ops const clk: sirf: make clk_ops const clk: spear: make clk_ops const CLK: SPEAr: make aux_clk_masks structures const CLK: SPEAr: make structure field and function argument as const
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Stephen Boyd authored
* clk-sunxi: clk: sunxi: explicitly request exclusive reset control clk: sunxi: fix build warning
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Stephen Boyd authored
* clk-hikey: clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: hi6220: mark clock cs_atb_syspll as critical
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Stephen Boyd authored
Merge tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk drivers updates from Thierry Reding: This contains cleanups and minor fixes for the Tegra clock driver. * tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() clk: tegra: dfll: Fix drvdata overwriting issue clk: tegra: Fix cclk_lp divisor register clk: tegra: Bump SCLK clock rate to 216 MHz clk: tegra: Use common definition of APBDMA clock gate clk: tegra: Correct parent of the APBDMA clock clk: tegra: Add AHB DMA clock entry clk: tegra: Mark APB clock as critical clk: tegra: Make tegra_clk_pll_params __ro_after_init clk: tegra: Fix sor1_out clock implementation clk: tegra: Use tegra_clk_register_periph_data() clk: tegra: Add peripheral clock registration helper clk: tegra: Check BPMP response return code dt-bindings: clock: tegra: Add sor1_out clock firmware: tegra: Propagate error code to caller
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Shawn Guo authored
Other than 'mmc_mux', 'clk_sdio0_ciu' uses a different parent mux clock. Let's add this mux clock as 'sdio0_mux', and correct the parent of 'clk_sdio0_ciu' to be it. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Markus Elfring authored
clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Reviewed-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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Zhong Kaihua authored
UART3 clock rate is doubled in previous commit. This error is not detected until recently a mezzanine board which makes real use of uart3 port (through LS connector of 96boards) was setup and tested on hi3660-hikey960 board. This patch changes clock source rate of clk_factor_uart3 to 100000000. Signed-off-by:
Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by:
Guodong Xu <guodong.xu@linaro.org> Signed-off-by:
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- 02 Nov, 2017 23 commits
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Adriana Reus authored
IMX7d does not have an M0 Core and this particular clock doesn't seem connected to anything else. Remove this entry from the CCM driver. Signed-off-by:
Adriana Reus <adriana.reus@nxp.com> Signed-off-by:
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Adriana Reus authored
The parent of OCRAM_CLK should be axi_main_root_clk and not axi_post_div. before: axi_src 1 1 332307692 0 0 axi_cg 1 1 332307692 0 0 axi_pre_div 1 1 332307692 0 0 axi_post_div 1 1 332307692 0 0 ocram_clk 0 0 332307692 0 0 main_axi_root_clk 1 1 332307692 0 0 after: axi_src 1 1 332307692 0 0 axi_cg 1 1 332307692 0 0 axi_pre_div 1 1 332307692 0 0 axi_post_div 1 1 332307692 0 0 main_axi_root_clk 1 1 332307692 0 0 ocram_clk 0 0 332307692 0 0 Reference Doc: i.MX 7D Reference Manual - Chap 5, p 516 (https://www.nxp.com/docs/en/reference-manual/IMX7DRM.pdf) Fixes: 8f6d8094 ("ARM: imx: add imx7d clk tree support") Signed-off-by: -
Philipp Zabel authored
Allowing the lcdif_pre_sel to propagate rate changes to its parent PLL allows more fine grained control over the LCDIF pixel clock rate. For example, the Innovision AT043TN24 LCD panel described in the imx6ul-14x14-evk device tree requires a 9 MHz pixel clock. Before this patch, the lcdif_pre_sel clock rate is fixed, and just setting the lcdif_pred and lcdif_podf dividers only allows to get as close as about 8.44 MHz: pll3 1 1 480000000 0 0 pll3_bypass 1 1 480000000 0 0 pll3_usb_otg 1 1 480000000 0 0 pll3_pfd1_540m 1 1 540000000 0 0 lcdif_pre_sel 1 1 540000000 0 0 lcdif_pred 1 1 67500000 0 0 lcdif_podf 1 1 8437500 0 0 lcdif_pix 1 1 8437500 0 0 Once lcdif_pre_sel is allowed to propagate rate requests to its parent, the actual pixel clock matches the requested value: pll3 1 1 480000000 0 0 pll3_bypass 1 1 480000000 0 0 pll3_usb_otg 1 1 480000000 0 0 pll3_pfd1_540m 1 1 288000000 0 0 lcdif_pre_sel 1 1 288000000 0 0 lcdif_pred 1 1 36000000 0 0 lcdif_podf 1 1 9000000 0 0 lcdif_pix 1 1 9000000 0 0 Signed-off-by:Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Sébastien Szymanski authored
On i.MX6 SoCs without VPU (in my case MCIMX6D4AVT10AC), the hdmi driver fails to probe: [ 2.540030] dwhdmi-imx 120000.hdmi: Unsupported HDMI controller (0000:00:00) [ 2.548199] imx-drm display-subsystem: failed to bind 120000.hdmi (ops dw_hdmi_imx_ops): -19 [ 2.557403] imx-drm display-subsystem: master bind failed: -19 That's because hdmi_isfr's parent, video_27m, is not correctly ungated. As explained in commit 5ccc248c ("ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate"), video_27m is gated by CCM_CCGR3[CG8]. On i.MX6 SoCs with VPU, the hdmi is working thanks to the CCM_CMEOR[mod_en_ov_vpu] bit which makes the video_27m ungated whatever is in CCM_CCGR3[CG8]. The issue can be reproduced by setting CCMEOR[mod_en_ov_vpu] to 0. Make the HDMI work in every case by setting hdmi_isfr's parent to mipi_core_cfg. Signed-off-by:
Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by:
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Rajendra Nayak authored
Add all RPM controlled clocks on msm8996 platform [srini: Fixed various issues with offsets and made names specific to msm8996] Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Linus Walleij authored
The RPM clocks were missing for MSM8660/APQ8060. For this to be completed we need to add a special fixed rate RPM clock that is used for the PLL4 on these SoCs. The rest of the clocks are pretty similar to the other supported platforms. The "active" clock pattern is mirrored in all the clocks. I guess that the PLL4 that clocks the LPASS is actually never used as "active only" since the low-power audio subsystem should be left on when the CPU goes to idle, so that it can be used as a stand-alone MP3 player type of device. The PLL4 seems to be enabled only on behalf of the booting LPASS Hexagon - which will cast its own vote once its booted - and as such we only configure the active state (meaning both states will have same configuration). The result is that PLL4 will be on from prepare() to unprepare() regardless of what the application CPU does. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
These compatible strings need to be added to extend support for the RPM CC to cover MSM8660/APQ8060. We also need to add enumberators to the include file for a few clocks that were missing. Cc: devicetree@vger.kernel.org Acked-by:
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Linus Walleij authored
The concept of "active" clocks is just explained in a bried comment in the device driver, let's explain it a bit more in the device tree bindings so everyone understands this. Cc: devicetree@vger.kernel.org Acked-by:
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Georgi Djakov authored
The RCGs ops for shared branches are not used now, so remove it. Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Ludovic Desroches authored
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. Signed-off-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by:
Ingo van Lil <inguin@gmx.de> Signed-off-by:
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Stephen Boyd authored
Now that we have devm APIs for the reset controller and of clk hw provider APIs we can remove the custom code here. Signed-off-by: -
Stephen Boyd authored
Sometimes we only have one of_clk_del_provider() call in driver error and remove paths, because we're missing a devm_of_clk_add_hw_provider() API. Introduce the API so we can convert drivers to use this and potentially reduce the amount of code needed to remove providers in drivers. Signed-off-by: -
Bhumika Goyal authored
Make these const as they are only stored in the init field of a clk_hw structure, which is const. Signed-off-by:
Bhumika Goyal <bhumirks@gmail.com> Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Bhumika Goyal authored
Make these const as they are either stored in the masks 'const' field of a clk_aux structure or passed to the function clk_register_aux having the argument as const. Signed-off-by:
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Bhumika Goyal authored
Make the masks field of clk_aux structure const as it do not modify the fields of the aux_clk_masks structure it points to. Make the struct aux_clk_masks *aux argument of the function clk_register_aux as const as the argument is only stored in the masks field of a clk_aux structure which is now made const. Signed-off-by:
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Philipp Zabel authored
Commit a53e35db ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-clk@vger.kernel.org Signed-off-by:
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Corentin LABBE authored
This patch fix the following build warning: drivers/clk/sunxi/clk-factors.c:279:14: warning: variable 'name' set but not used [-Wunused-but-set-variable] Fixes: 4cbeaebb ("clk: sunxi: factors: Add unregister function") Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by:
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- 01 Nov, 2017 6 commits
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Leo Yan authored
Clock cs_atb_syspll is pll used for coresight trace bus; when clock cs_atb_syspll is disabled and operates its child clock node cs_atb results in system hang. So mark clock cs_atb_syspll as critical to keep it enabled. Cc: Guodong Xu <guodong.xu@linaro.org> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@linaro.org
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Nicolin Chen authored
Below is the call trace of tegra210_init_pllu() function: start_kernel() -> time_init() --> of_clk_init() ---> tegra210_clock_init() ----> tegra210_pll_init() -----> tegra210_init_pllu() Because the preemption is disabled in the start_kernel before calling time_init, tegra210_init_pllu is actually in an atomic context while it includes a readl_relaxed_poll_timeout that might sleep. So this patch just changes this readl_relaxed_poll_timeout() to its atomic version. Signed-off-by:
Nicolin Chen <nicoleotsuka@gmail.com> Acked-By:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Nicolin Chen authored
Both tegra124-dfll and clk-dfll are using platform_set_drvdata to set drvdata of the exact same pdev while they use different pointers for the drvdata. Once the drvdata has been overwritten by tegra124-dfll, clk-dfll will never get its td pointer as it expects. Since tegra124-dfll merely needs its soc pointer in its remove function, this patch fixes the bug by removing the overwriting in the tegra124-dfll file and letting the tegra_dfll_unregister return an soc pointer for it. Signed-off-by:
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Michał Mirosław authored
According to comments in code and common sense, cclk_lp uses its own divisor, not cclk_g's. Fixes: b08e8c0e ("clk: tegra: add clock support for Tegra30") Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-By:
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Dmitry Osipenko authored
AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Acked-By:
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Dmitry Osipenko authored
The APBDMA clock is defined in the common clock gates table that is used by Tegra30+. Tegra20 can use it too, let's remove the custom definition and use the common one. Signed-off-by:
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