- 18 Apr, 2019 2 commits
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Lucas Stach authored
This adds support to the PHY driver to power up/down the VBUS voltage rail at the appropriate times. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
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Lucas Stach authored
Add a vbus supply regulator phandle, so the PHY can enable the VBUS voltage rail when powering up. Signed-off-by:
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- 17 Apr, 2019 38 commits
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Marc Gonzalez authored
Documentation for this PHY, and the proper configuration settings, is *not* publicly available. Therefore the initialization sequence is copied wholesale from downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372Reviewed-by:
Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by:
Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by:
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Roger Quadros authored
Add support to select all 16 CLKSEL combinations that are shown in "SerDes Reference Clock Distribution" in AM65 TRM. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
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Kishon Vijay Abraham I authored
Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 will be added later. SERDES in am654x has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. [rogerq@ti.com: Fix boot lockup caused by accessing a structure member (hw->init) allocated in stack of probe() and accessed in get_parent] [rogerq@ti.com: Fix "Failed to find the parent" warnings] Signed-off-by:
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Kishon Vijay Abraham I authored
AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: -
Kishon Vijay Abraham I authored
PHY drivers may try to access PHY registers in the ->reset() callback. Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback so that the PHY drivers don't have to enable clocks by themselves before accessing PHY registers. Signed-off-by: -
Kishon Vijay Abraham I authored
Add a new phy_ops *release* invoked when the consumer relinquishes the PHY using phy_put/devm_phy_put. The initializations done by the PHY driver in of_xlate call back can be can be cleaned up here. Signed-off-by: -
Chunfeng Yun authored
Use devm_clk_get_optional() to get optional clock Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Chunfeng Yun authored
Use devm_clk_get_optional() to get optional clock Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by:
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Chunfeng Yun authored
Use devm_clk_get_optional() to get optional clock Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by:
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Chunfeng Yun authored
Use devm_clk_get_optional() to get optional clock Signed-off-by:
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Yoshihiro Shimoda authored
Since the previous code enabled/disabled the irqs both OHCI and EHCI, it is possible to cause unexpected interruptions. To avoid this, this patch creates multiple phy instances from phandle and enables/disables independent irqs by the instances. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Tested-by:
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Yoshihiro Shimoda authored
To implement multiple phy instances in the future, this patch uses pdev's device pointer on dev_vdbg() instead of the phy's device pointer. Signed-off-by:
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Yoshihiro Shimoda authored
To have the detailed property on each PHY specifier, this patch revises the #phy-cells property. Signed-off-by:
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Biju Das authored
This patch adds support for r8a77470 (RZ/G1C). We can reuse this driver for initializing timing/interrupt generation registers. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
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Biju Das authored
This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1 and R-Car Gen2/3, USB Host needs to deassert the pll reset. Signed-off-by:
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Biju Das authored
Document RZ/G1C (R8A77470) SoC bindings. For RZ/G1C, this driver is used to enable interrupt generation and initializing timing registers which is part of phy_init code. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Biju Das authored
Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470) USB PHY is similar to the R-Car Gen2 family, but has the below feature compared to other RZ/G1 and R-Car Gen2/3 SoCs It has a shared pll reset for usbphy0/usbphy1 and this register reside in usbphy0 block. Signed-off-by:
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Roger Quadros authored
TRM [1] mentions that we need to power up PCIESS_PHY_TX and PCIESS_PHY_RX before configuring PCIe_PHY_RX SCP settings. See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence". [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdfSigned-off-by:
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Roger Quadros authored
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdfSigned-off-by:
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Roger Quadros authored
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdfSigned-off-by:
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Roger Quadros authored
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by:
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Colin Ian King authored
There seems to be a missing bit-wise or operator when setting val, fix this by adding it in. Fixes: 2796ceb0 ("phy: ti-pipe3: Update pcie phy settings") Cc: stable@vger.kernel.org # v4.19+ Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Stanley Chu authored
Add UFS M-PHY driver on MediaTek chipsets. Signed-off-by:
Stanley Chu <stanley.chu@mediatek.com> Reviewed-by:
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Stanley Chu authored
Add UFS M-PHY node document for MediaTek SoC chips. Signed-off-by:
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Christoph Muellner authored
This patch documents the new proprty drive-impedance-ohm for Rockchip's eMMC PHY node. Signed-off-by:
Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by:
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by:
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Christoph Muellner authored
The rockchip-emmc PHY can be configured with different drive impedance values. Currenlty a value of 50 Ohm is hard coded into the driver. This patch introduces the DTS property 'drive-impedance-ohm' for the rockchip-emmc phy node, which uses the value from the DTS to setup the drive impedance accordingly. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Evan Green authored
The phy code was using implicit sequencing between the PHY driver and the UFS driver to implement certain hardware requirements. Specifically, the PHY reset register in the UFS controller needs to be deasserted before serdes start occurs in the PHY. Before this change, the code was doing this by utilizing the two phy callbacks, phy_init() and phy_poweron(), as "init step 1" and "init step 2", where the UFS driver would deassert reset between these two steps. This makes it challenging to power off the regulators in suspend, as regulators are initialized in init, not in poweron(), but only poweroff() is called during suspend, not exit(). For UFS, move the actual firing up of the PHY to phy_poweron() and phy_poweroff() callbacks, rather than init()/exit(). UFS calls phy_poweroff() during suspend, so now all clocks and regulators for the phy can be powered down during suspend. QMP is a little tricky because the PHY is also shared with PCIe and USB3, which have their own definitions for init() and poweron(). Rename the meaty functions to _enable() and _disable() to disentangle from the PHY core names, and then create two different ops structures: one for UFS and one for the other PHY types. In phy-qcom-ufs, remove the 'is_powered_on' and 'is_started' guards, as the generic PHY code does the reference counting. The 14/20nm-specific init functions get collapsed into the generic power_on() function, with the addition of a calibrate() callback specific to 14/20nm. Signed-off-by:
Evan Green <evgreen@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Evan Green authored
Move the PHY reset from ufs-qcom into the respective PHYs. This will allow us to merge the two phases of UFS PHY initialization. Signed-off-by:
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Evan Green authored
Expose a reset controller that the phy will later use to control its own PHY reset in the UFS controller. This will enable the combining of PHY init functionality into a single function. Signed-off-by:
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Evan Green authored
Add a resets property to the PHY that represents the PHY reset register in the UFS controller itself. This better describes the complete specification of the PHY, and allows the PHY to perform its initialization in a single function, rather than relying on back-channel sequencing of initialization through the PHY framework. Signed-off-by:
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Evan Green authored
Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by:
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Evan Green authored
Enable Qualcomm UFS controllers to expose the PHY reset via a reset controller. Signed-off-by:
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Neil Armstrong authored
This adds support for the shared USB3 + PCIE PHY found in the Amlogic G12A SoC Family. It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of the board. Selection is done by the #phy-cells, making the mode static and exclusive. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
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Neil Armstrong authored
This adds support for the USB2 PHY found in the Amlogic G12A SoC Family. It supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. Signed-off-by:
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Neil Armstrong authored
Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings. This PHY can provide exclusively USB3 or PCIE support on shared I/Os. Signed-off-by:
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Neil Armstrong authored
Add the Amlogic G12A Family USB2 OTG PHY Bindings The PHY can work in host or peripheral modes depending on it's position. Configuration of the mode is part of the USBCTRL registers which are outside of the PHY registers. Signed-off-by:
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Srinath Mannam authored
USB PHY driver supports two types of stingray USB PHYs - Type 1 is a combo PHY contains two PHYs, one SS and one HS. - Type 2 is a single HS PHY. These two PHY versons support both Generic xHCI host controller driver and BDC Broadcom device controller driver. Signed-off-by:
Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by:
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Srinath Mannam authored
Add DT binding document for Stingray USB PHY. Signed-off-by:
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