- 05 Nov, 2012 1 commit
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Stephen Warren authored
This should make it easier to delete or move <mach/*.h>; something that is useful for single-zImage. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 13 Sep, 2012 1 commit
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Joseph Lo authored
The tegra_cpu_car_ops provide the interface for CPU to control it's clock gating and reset status. The other drivers should use this for CPU control. And should not directly access CAR registers to control CPU. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 06 Sep, 2012 2 commits
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Prashant Gaikwad authored
Remove Tegra legacy clock framework code. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add Tegra platform specific clock structure clk_tegra and some helper functions for generic clock framework. struct clk_tegra is the single strcture used for all types of clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 08 May, 2012 1 commit
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Shawn Guo authored
Cc: Colin Cross <ccross@android.com> Cc: Olof Johansson <olof@lixom.net> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org>
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- 06 Feb, 2012 1 commit
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Peter De Schrijver authored
Add support for new clock framework features implemented in tegra30. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- 20 Dec, 2011 1 commit
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Stephen Warren authored
tegra_init_clock() is written to call tegra2_init_clocks(), which only exists if Tegra20 support is enabled. This breaks the build of a Tegra30-only kernel. tegra_init_clock() isn't actually used any more; tegra20_init_early() calls tegra2_init_clocks() directly. So, just delete this function. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- 18 Dec, 2011 1 commit
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Peter De Schrijver authored
Rework the tegra20 clock code to support multiple tegra variants : * remove tegra2_periph_reset_assert/tegra2_periph_reset_deassert. This functionality should be in clock.c. * remove tegra_sdmmc_tap_delay and export tegra2_sdmmc_tap_delay directly. This feature is handled inside the sdmmc block from tegra30 onwards. So there is no need for support in the clock code beyond tegra20. There are no in tree users of this function. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Colin Cross <ccross@android.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- 21 Jul, 2011 1 commit
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Al Viro authored
Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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- 22 Feb, 2011 1 commit
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Colin Cross authored
Call the clock's round_rate op, if it exists, before calling the set_rate op. This will help later when dvfs is added, dvfs needs to know what the final rate will be before the frequency changes. Also requires fixes to the round rate functions to ensure calling round rate and then set rate will not cause the frequency to be rounded down twice. When picking clock divider values, the clock framework picks the closest frequency that is lower than the requested frequency. If the new frequency calculated from the divider value is rounded down, and then passed to set_rate, it will get rounded down again, possibly resulting in a frequency two steps lower than the original requested frequency. Fix the problem by rounding up when calculating the frequency coming out of a clock divider, so if that frequency is requested again, the same divider value will be picked. Signed-off-by:
Colin Cross <ccross@android.com> Acked-by:
Olof Johansson <olof@lixom.net>
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- 21 Feb, 2011 6 commits
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Colin Cross authored
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Colin Cross <ccross@android.com>
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Colin Cross authored
Remove unnecessary uses of #ifdef CONFIG_DEBUG_FS Convert bool assignments from 1 to true Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Colin Cross <ccross@android.com>
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Colin Cross authored
Give each clock its own lock, and remove all lock traversals from parent to child clocks to prevent AB-BA deadlocks. This brings the locking in line with the common struct clk patches and should make conversion simple. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Colin Cross <ccross@android.com>
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Colin Cross authored
The existing version did not extend well to core dvfs, drop it for now until the new clk api with clk_prepare and clk_unprepare is ready and non-atomic clocks are possible. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Colin Cross <ccross@android.com>
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Colin Cross authored
Assume that any clock that has no enable op is always on. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Colin Cross <ccross@android.com>
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Colin Cross authored
Drop the unnecessary pr_debug calls to avoid having to maintain them. Acked-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
Colin Cross <ccross@android.com>
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- 26 Nov, 2010 1 commit
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Jean-Christop PLAGNIOL-VILLARD authored
factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by:
Paul Mundt <lethal@linux-sh.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- 22 Oct, 2010 1 commit
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Colin Cross authored
- Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by:
Colin Cross <ccross@android.com>
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- 05 Aug, 2010 1 commit
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Colin Cross authored
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by:
Colin Cross <ccross@android.com>
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